In-place AC measurements of the signal gain and substrate sensitivity of differential pair transistors of an analog amplifier are combined with DC characterization of the threshold voltage (Vth) of the same transistors. An on-chip continuous time waveform monitoring technique enables in-place matrix measurements of differential pair transistors with a variety of channel sizes and geometry, allowing the wide coverage of experiments about the transistor-level physical layout dependency of substrate noise response. A prototype test structure uses a 90-nm CMOS technology and demonstrates the geometry-dependent variation of substrate sensitivity of transistors in operation.

Device design to reduce the abnormal operation due to the floating body effect was investigated for 0.2µm fully depleted SOI-MOSFETs, by use of a two-dimensional device simulator. It was found that the critical drain voltage and the critical multiplication factor for the floating body effect strongly depend on the potential profile which is related to the doping concentration. Based on simulation results, a nonuniformly doped structure is proposed for optimizing the potential profile to reduce the floating body effect. The applicable voltage of this structure was found to be 40% higher than that of the uniformly doped structure. A simple model is also derived to explain the above result.

A continuous-time waveform monitoring technique for quality on-chip power noise measurements features matched probing performance among a variety of voltage domains of interest in a VLSI circuit, covering digital Vdd, analog Vdd, as well as at Vss, and multiple probing capability at various locations on power planes. A calibration flow eliminates the offset as well as gain errors among probing channels. The consistency of waveforms acquired by the proposed continuous-time monitoring and sampled-time precise digitization techniques is ensured. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with 200 mV at 2.5 V, 1.0 V, and 0.0 V, respectively, with less than 4 mV deviation among 240 probing channels.

A uniform raised-salicide technology has been investigated using both uniform selective-epitaxial-growth (SEG) silicon and salicide films, to reduce a junction leakage current of shallow source/drain (S/D) regions for high-performance CMOS devices. The uniform SEG-Si film without pits is formed by using a wet process, which is a carbon-free oxide removal only using a dilute hydrofluoric acid (DHF) dipping, prior to the Si-SEG process. After a titanium-salicide formation using a conventional two-step salicide process, this uniform SEG-Si film achieves good S/D junction characteristics. The uniform titanium-salicide film without bowing into a silicon is formed by a smaller Ti/SEG-Si thickness ratio, which results in a low sheet resistance of 5 Ω/sq. without a narrow-line effect. Furthermore, the drive current is maximized by this raised-salicide film using a Ti/SEG-Si thickness ratio of 1.0.

A single tone pseudo-noise generator with a harmonic-eliminated waveform is proposed for measuring noise tolerance of analog IPs. In the waveform, the harmonics up to the thirteenth are eliminated by combining seven rectangular waves with 22.5-degree spacing phases. The proposed waveform includes only high region frequency harmonic components, which are easily suppressed by a low-order filter. This characteristic enables simple circuit implementation for a sine wave generator. In the circuit, the harmonic eliminated waveform generator is combined with a current controlled oscillator and a frequency adjustment circuit. The single tone pseudo-noise generator can generate power line noise from 20 MHz to 220 MHz with 1 MHz steps. The SFDR of 40 dB is obtained at the noise frequency of 100 MHz. The circuit enables the measurement of frequency response characteristics measurements such as PSRR.

The response of differential pairs against low-frequency substrate voltage variation is captured in a combined transistor and substrate network models. The model generation is regularized for variation of transistor geometries including channel sizes, fingering and folding, and the placements of guard bands. The expansion of the models for full-chip substrate noise analysis is also discussed. The substrate sensitivity of differential pairs is evaluated through on-chip substrate coupling measurements in a 90 nm CMOS technology with more than 64 different geometries and operating conditions. The trends and strengths of substrate sensitivity are shown to be well consistent between simulation and measurements.

Surface-channel PMOSFETs are suitable for use in the quarter micron CMOS devices. For surface-channel PMOSFETs with p+ poly-Si gates, boron penetration and hot-carrier effects were investigated. When the annealing temperature is higher and the gate oxide is thinner, a larger threshold voltage shift was observed for p+ poly-Si PMOSFETs, because of boron penetration. Furthermore, PMOSFETs with BF2-implanted gates cause larger boron penetration than those with Boron-implanted gates. Howerer, the PMOSFET lifetime, determined by hot-carrier reliability, does not depend on the degree of boron penetration. Instead, it depends on doping species, that is, BF2 and Boron. PMOSFETs with BF2-implanted gates have about 100 times longer lifetime than those with Boron-implanted gates. The main reason for the longer lifetime of BF2-doped PMOSFETs is the incorporation of fluorine in the gate oxide of the PMOSFET with the BF2-implanted gate, resulting in the smaller electron trapping in the gate oxide. The maximun allowed supply voltage,based on the hot-carrier reliability, is higher than4V for sub-half micron PMOSFETs with BF2- or Boron-implanted poly Si gates.

This paper describes an ultralow-power multi-threshold (MT) CMOS/SOI circuit technique that mainly uses fully-depleted MOSFETs. The MTCMOS/SOI circuit, which combines fully-depleted low- and medium-Vth CMOS/SOI logic gates and high-Vth power-switch transistors, makes it possible to lower the supply voltage to 0.5 V and reduce the power dissipation of LSIs to the 1-mW level. We overview some MTCMOS/SOI digital and analog components, such as a CPU, memory, analog/RF circuit and DC-DC converter for an ultralow-power mobile system. The validity of the ultralow-voltage MTCMOS/SOI circuits is confirmed by the demonstration of a self-powered 300-MHz-band short-range wireless system. A 1-V SAW oscillator and a switched-capacitor-type DC-DC converter in the transmitter makes possible self-powered transmission by the heat from a hand. In the receiver, a 0.5-V digital controller composed of a 8-bit CPU, 256-kbit SRAM, and ROM also make self-powered operation under illumination possible.