AlGaAs/GaAs HBT ICs for high bit-rate optical transmission systems, such as preamplifier, D-F/F, differential amplifier, and laser driver, have been newly developed using the hetero guard-ring fully self-aligned HBT (HGFST) fabrication process. In this process, the emitter mesa is ECR-RIBE dry etched using a thick emitter-metal system of WSi and Ti-Pt-Au as etching mask, and a hetero guard-ring composed of a depleted AlGaAs layer is fabricated on p GaAs extrinsic base regions. This process results in highly uniform HBT characteristics. The preamplifier IC exhibits a DC to 18.5-GHz transimpedance bandwidth with a transimpedance gain of 49 dBΩ. The rise time and fall time for the D-F/F IC are 30 and 23 ps, respectively. The laser driver IC has a 40-mAp-p output current swing. The differential amplifier exhibits a DC to 12.1-GHz bandwidth with a 14.2-dB power gain.

A low voltage operational active inductor circuit is attractive for spiral-inductor-less LNA because of realizing high gain and low voltage operation simultaneously. In this paper, a simply structured low-voltage operational active inductor to enhance the amplifier gain is introduced and analyzed. This active inductor, which utilizes a transistor load operated in the triode region and a source follower, features a small DC voltage drop suitable for low voltage LNAs. An LNA using the active inductor load was designed with an input matching circuit using 90 nm CMOS technology. The LNA tuned to 2.4 GHz operation has 19.5 dB of the internal gain. In addition, the frequency characteristics are easily varied by changing the capacitance value in the active inductor circuit. The core circuit occupies only 0.0026 mm2 and consumes 2.8 mW with 1.2 V supply voltage.

This report describes AlGaAs/GaAs HBT ICs for 20-Gb/s optical transmission, the preamplifier and optical modulator driver circuits, and those ICs for 10-Gb/s clock extraction circuits, the rectifier and phase shifter circuits. These ICs were fabricated using our developed hetero guard-ring fully self-aligned HBT (HG-FST) fabrication process. The Pt-Ti-Pt-Au multimetal system was also used as a base ohmic metal to reduce base contact resistance, and a high fmax of 105 GHz was obtained. Good results in the HBT IC microwave performances were achieved from the on-wafer measurements. The preamplifiers exhibited the broad bandwidth of 20. 9 GHz. The optical modulator driver performed a sufficiently large output-voltage swing of 4-VP-P at a 20-Gb/s data rate. The rectifier and the phase shifter circuits achieved good operations at 10-Gb/s. These results suggest that these HBT ICs can be applied to 20-Gb/s optical transmission and 10-Gb/s clock extraction systems.

A single tone pseudo-noise generator with a harmonic-eliminated waveform is proposed for measuring noise tolerance of analog IPs. In the waveform, the harmonics up to the thirteenth are eliminated by combining seven rectangular waves with 22.5-degree spacing phases. The proposed waveform includes only high region frequency harmonic components, which are easily suppressed by a low-order filter. This characteristic enables simple circuit implementation for a sine wave generator. In the circuit, the harmonic eliminated waveform generator is combined with a current controlled oscillator and a frequency adjustment circuit. The single tone pseudo-noise generator can generate power line noise from 20 MHz to 220 MHz with 1 MHz steps. The SFDR of 40 dB is obtained at the noise frequency of 100 MHz. The circuit enables the measurement of frequency response characteristics measurements such as PSRR.

In this paper, we propose two methods to estimate clock jitter caused by power supply noise in a LSI (Large-Scale Integrated circuit). One of the methods enables estimation of clock jitter at the initial design stage before floor-planning. The other method reduces simulation time of clock distribution network to analyze clock jitter at the design verification stage after place-and-route of the chip. For an example design, the relative difference between clock jitter estimated at the initial design stage and that of the design verification stage is 23%. The example result also shows that the proposed method for the verification stage is about 24 times faster than the conventional one to analyze clock jitter.