IEICE TRANSACTIONS on Fundamentals
Fast Methods to Estimate Clock Jitter due to Power Supply Noise
Summary :
In this paper, we propose two methods to estimate clock jitter caused by power supply noise in a LSI (Large-Scale Integrated circuit). One of the methods enables estimation of clock jitter at the initial design stage before floor-planning. The other method reduces simulation time of clock distribution network to analyze clock jitter at the design verification stage after place-and-route of the chip. For an example design, the relative difference between clock jitter estimated at the initial design stage and that of the design verification stage is 23%. The example result also shows that the proposed method for the verification stage is about 24 times faster than the conventional one to analyze clock jitter.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.4 pp.741-747
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e90-a.4.741
- Type of Manuscript
- Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- Category
Authors
Keyword
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Koutaro HACHIYA, Takayuki OHSHIMA, Hidenari NAKASHIMA, Masaaki SODA, Satoshi GOTO, "Fast Methods to Estimate Clock Jitter due to Power Supply Noise" in IEICE TRANSACTIONS on Fundamentals,
vol. E90-A, no. 4, pp. 741-747, April 2007, doi: 10.1093/ietfec/e90-a.4.741.
Abstract: In this paper, we propose two methods to estimate clock jitter caused by power supply noise in a LSI (Large-Scale Integrated circuit). One of the methods enables estimation of clock jitter at the initial design stage before floor-planning. The other method reduces simulation time of clock distribution network to analyze clock jitter at the design verification stage after place-and-route of the chip. For an example design, the relative difference between clock jitter estimated at the initial design stage and that of the design verification stage is 23%. The example result also shows that the proposed method for the verification stage is about 24 times faster than the conventional one to analyze clock jitter.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.4.741/_p
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@ARTICLE{e90-a_4_741,
author={Koutaro HACHIYA, Takayuki OHSHIMA, Hidenari NAKASHIMA, Masaaki SODA, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Fast Methods to Estimate Clock Jitter due to Power Supply Noise},
year={2007},
volume={E90-A},
number={4},
pages={741-747},
abstract={In this paper, we propose two methods to estimate clock jitter caused by power supply noise in a LSI (Large-Scale Integrated circuit). One of the methods enables estimation of clock jitter at the initial design stage before floor-planning. The other method reduces simulation time of clock distribution network to analyze clock jitter at the design verification stage after place-and-route of the chip. For an example design, the relative difference between clock jitter estimated at the initial design stage and that of the design verification stage is 23%. The example result also shows that the proposed method for the verification stage is about 24 times faster than the conventional one to analyze clock jitter.},
keywords={},
doi={10.1093/ietfec/e90-a.4.741},
ISSN={1745-1337},
month={April},}
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TY - JOUR
TI - Fast Methods to Estimate Clock Jitter due to Power Supply Noise
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 741
EP - 747
AU - Koutaro HACHIYA
AU - Takayuki OHSHIMA
AU - Hidenari NAKASHIMA
AU - Masaaki SODA
AU - Satoshi GOTO
PY - 2007
DO - 10.1093/ietfec/e90-a.4.741
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2007
AB - In this paper, we propose two methods to estimate clock jitter caused by power supply noise in a LSI (Large-Scale Integrated circuit). One of the methods enables estimation of clock jitter at the initial design stage before floor-planning. The other method reduces simulation time of clock distribution network to analyze clock jitter at the design verification stage after place-and-route of the chip. For an example design, the relative difference between clock jitter estimated at the initial design stage and that of the design verification stage is 23%. The example result also shows that the proposed method for the verification stage is about 24 times faster than the conventional one to analyze clock jitter.
ER -
English
