A 1.5 V 8 mW BiCMOS video A/D converter has been developed by using a BiCMOS pumping comparator. Combining Bipolar high-speed and good-matching characteristics with CMOS switched capacitor techniques, this A/D converter is suitable for use in battery-operated multimedia terminals.

A low voltage operational active inductor circuit is attractive for spiral-inductor-less LNA because of realizing high gain and low voltage operation simultaneously. In this paper, a simply structured low-voltage operational active inductor to enhance the amplifier gain is introduced and analyzed. This active inductor, which utilizes a transistor load operated in the triode region and a source follower, features a small DC voltage drop suitable for low voltage LNAs. An LNA using the active inductor load was designed with an input matching circuit using 90 nm CMOS technology. The LNA tuned to 2.4 GHz operation has 19.5 dB of the internal gain. In addition, the frequency characteristics are easily varied by changing the capacitance value in the active inductor circuit. The core circuit occupies only 0.0026 mm2 and consumes 2.8 mW with 1.2 V supply voltage.

This paper proposes two novel Multi-bit Delta-Sigma Modulator (Δ Σ M) architectures based on a Dual-Quantization architecture. By using multi-bit quantization with single-bit feedback, Both eliminate the need for a multi-bit digital-to-analog converter (DAC) in the feedback loop. The first is a Digital quantization-Error Canceling Multi-bit (DECM)-Δ Σ M architecture that is able to achieve high resolution at a low oversampling ratio (OSR) because, by adjusting the coefficients of both analog and digital circuits, it is able to cancel completely the quantization error injected into the single-bit quantizer. Simulation results show that a signal-to-quantization-noise ratio of 90 dB is obtained with 3rd order 5-bit quantization DECM-Δ Σ M at an OSR of 32. The second architecture, an analog-to-digital mixed (ADM)-Δ Σ M architecture, uses digital integrators in place of the analog integrator circuits used in the Δ Σ M. This architecture reduces both die area and power dissipation. We estimate that a (2+2)-th order ADM-Δ Σ M with two analog-integrators and two digital-integrators will reduce the area of a 4-th order Δ Σ M by 15%.

In this paper, we briefly review the recent research on CMOS gigahertz-rate communication circuits. Then, we describe design innovations we have made to overcome limitations on communication speed. Using 0. 25-µm CMOS technology, we developed a 4.25-Gb/s Fibre Channel transceiver that features an asynchronous tree-type 1 : 8 demultiplexer and an 8-bit-to-10-bit frequency-conversion architecture. And using 0. 15-µm CMOS technology, we developed an 11. 8-GHz frequency divider that introduces the novel idea of a hysteresis-controlled latch (HC-latch). With these results, we discuss high-speed LSI design issues and future prospects.