IEICE TRANSACTIONS on Electronics
Design Innovations for Multi-Gigahertz-Rate Communication Circuits with Deep-Submicron CMOS Technology
Summary :
In this paper, we briefly review the recent research on CMOS gigahertz-rate communication circuits. Then, we describe design innovations we have made to overcome limitations on communication speed. Using 0. 25-µm CMOS technology, we developed a 4.25-Gb/s Fibre Channel transceiver that features an asynchronous tree-type 1 : 8 demultiplexer and an 8-bit-to-10-bit frequency-conversion architecture. And using 0. 15-µm CMOS technology, we developed an 11. 8-GHz frequency divider that introduces the novel idea of a hysteresis-controlled latch (HC-latch). With these results, we discuss high-speed LSI design issues and future prospects.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E82-C No.3 pp.428-437
- Publication Date
- 1999/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
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Masakazu KURISU, Muneo FUKAISHI, Hiroshi ASAZAWA, Masato NISHIKAWA, Kazuyuki NAKAMURA, Michio YOTSUYANAGI, "Design Innovations for Multi-Gigahertz-Rate Communication Circuits with Deep-Submicron CMOS Technology" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 3, pp. 428-437, March 1999, doi: .
Abstract: In this paper, we briefly review the recent research on CMOS gigahertz-rate communication circuits. Then, we describe design innovations we have made to overcome limitations on communication speed. Using 0. 25-µm CMOS technology, we developed a 4.25-Gb/s Fibre Channel transceiver that features an asynchronous tree-type 1 : 8 demultiplexer and an 8-bit-to-10-bit frequency-conversion architecture. And using 0. 15-µm CMOS technology, we developed an 11. 8-GHz frequency divider that introduces the novel idea of a hysteresis-controlled latch (HC-latch). With these results, we discuss high-speed LSI design issues and future prospects.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_3_428/_p
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@ARTICLE{e82-c_3_428,
author={Masakazu KURISU, Muneo FUKAISHI, Hiroshi ASAZAWA, Masato NISHIKAWA, Kazuyuki NAKAMURA, Michio YOTSUYANAGI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design Innovations for Multi-Gigahertz-Rate Communication Circuits with Deep-Submicron CMOS Technology},
year={1999},
volume={E82-C},
number={3},
pages={428-437},
abstract={In this paper, we briefly review the recent research on CMOS gigahertz-rate communication circuits. Then, we describe design innovations we have made to overcome limitations on communication speed. Using 0. 25-µm CMOS technology, we developed a 4.25-Gb/s Fibre Channel transceiver that features an asynchronous tree-type 1 : 8 demultiplexer and an 8-bit-to-10-bit frequency-conversion architecture. And using 0. 15-µm CMOS technology, we developed an 11. 8-GHz frequency divider that introduces the novel idea of a hysteresis-controlled latch (HC-latch). With these results, we discuss high-speed LSI design issues and future prospects.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Design Innovations for Multi-Gigahertz-Rate Communication Circuits with Deep-Submicron CMOS Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 428
EP - 437
AU - Masakazu KURISU
AU - Muneo FUKAISHI
AU - Hiroshi ASAZAWA
AU - Masato NISHIKAWA
AU - Kazuyuki NAKAMURA
AU - Michio YOTSUYANAGI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1999
AB - In this paper, we briefly review the recent research on CMOS gigahertz-rate communication circuits. Then, we describe design innovations we have made to overcome limitations on communication speed. Using 0. 25-µm CMOS technology, we developed a 4.25-Gb/s Fibre Channel transceiver that features an asynchronous tree-type 1 : 8 demultiplexer and an 8-bit-to-10-bit frequency-conversion architecture. And using 0. 15-µm CMOS technology, we developed an 11. 8-GHz frequency divider that introduces the novel idea of a hysteresis-controlled latch (HC-latch). With these results, we discuss high-speed LSI design issues and future prospects.
ER -
English
