IEICE TRANSACTIONS on Electronics
Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation
Summary :
The response of differential pairs against low-frequency substrate voltage variation is captured in a combined transistor and substrate network models. The model generation is regularized for variation of transistor geometries including channel sizes, fingering and folding, and the placements of guard bands. The expansion of the models for full-chip substrate noise analysis is also discussed. The substrate sensitivity of differential pairs is evaluated through on-chip substrate coupling measurements in a 90 nm CMOS technology with more than 64 different geometries and operating conditions. The trends and strengths of substrate sensitivity are shown to be well consistent between simulation and measurements.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E96-C No.6 pp.884-893
- Publication Date
- 2013/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E96.C.884
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
Satoshi TAKAYA
Kobe University
Yoji BANDO
Kobe University
Toru OHKAWA
MIRAI-Selete
Toshiharu TAKARAMOTO
MIRAI-Selete
Toshio YAMADA
MIRAI-Selete
Masaaki SOUDA
MIRAI-Selete
Shigetaka KUMASHIRO
MIRAI-Selete
Tohru MOGAMI
MIRAI-Selete
Makoto NAGATA
Kobe University
Keyword
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Satoshi TAKAYA, Yoji BANDO, Toru OHKAWA, Toshiharu TAKARAMOTO, Toshio YAMADA, Masaaki SOUDA, Shigetaka KUMASHIRO, Tohru MOGAMI, Makoto NAGATA, "Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 6, pp. 884-893, June 2013, doi: 10.1587/transele.E96.C.884.
Abstract: The response of differential pairs against low-frequency substrate voltage variation is captured in a combined transistor and substrate network models. The model generation is regularized for variation of transistor geometries including channel sizes, fingering and folding, and the placements of guard bands. The expansion of the models for full-chip substrate noise analysis is also discussed. The substrate sensitivity of differential pairs is evaluated through on-chip substrate coupling measurements in a 90 nm CMOS technology with more than 64 different geometries and operating conditions. The trends and strengths of substrate sensitivity are shown to be well consistent between simulation and measurements.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.884/_p
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@ARTICLE{e96-c_6_884,
author={Satoshi TAKAYA, Yoji BANDO, Toru OHKAWA, Toshiharu TAKARAMOTO, Toshio YAMADA, Masaaki SOUDA, Shigetaka KUMASHIRO, Tohru MOGAMI, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation},
year={2013},
volume={E96-C},
number={6},
pages={884-893},
abstract={The response of differential pairs against low-frequency substrate voltage variation is captured in a combined transistor and substrate network models. The model generation is regularized for variation of transistor geometries including channel sizes, fingering and folding, and the placements of guard bands. The expansion of the models for full-chip substrate noise analysis is also discussed. The substrate sensitivity of differential pairs is evaluated through on-chip substrate coupling measurements in a 90 nm CMOS technology with more than 64 different geometries and operating conditions. The trends and strengths of substrate sensitivity are shown to be well consistent between simulation and measurements.},
keywords={},
doi={10.1587/transele.E96.C.884},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation
T2 - IEICE TRANSACTIONS on Electronics
SP - 884
EP - 893
AU - Satoshi TAKAYA
AU - Yoji BANDO
AU - Toru OHKAWA
AU - Toshiharu TAKARAMOTO
AU - Toshio YAMADA
AU - Masaaki SOUDA
AU - Shigetaka KUMASHIRO
AU - Tohru MOGAMI
AU - Makoto NAGATA
PY - 2013
DO - 10.1587/transele.E96.C.884
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2013
AB - The response of differential pairs against low-frequency substrate voltage variation is captured in a combined transistor and substrate network models. The model generation is regularized for variation of transistor geometries including channel sizes, fingering and folding, and the placements of guard bands. The expansion of the models for full-chip substrate noise analysis is also discussed. The substrate sensitivity of differential pairs is evaluated through on-chip substrate coupling measurements in a 90 nm CMOS technology with more than 64 different geometries and operating conditions. The trends and strengths of substrate sensitivity are shown to be well consistent between simulation and measurements.
ER -
English
