A continuous-time (CT) ΔΣ analog-to-digital converter (ADC) is a high resolution, wide-bandwidth ADC. A Gm-C filter is suitable for low power consumption and its frequency characteristics for a loop filter of the ADC. However, in practice, distortion generated in the Gm-C filter degrades the SNDR of the ADC, therefore a high-linearity Gm-cell with low power consumption is needed. A flipped voltage follower (FVF) Gm-cell is also used as a high-linearity Gm-cell, but distortion is caused by variation of drain-source voltage of its input transistors. In this paper, a new high-linearity Gm-cell is proposed for the CT ΔΣ ADC in order to address this problem. A proposed topology is a combination of a FVF and a cascode topology. The inserted transistors in the proposed Gm-cell behave as cascode transistors, therefore the drain-source voltage variation of the input transistor and a PMOS transistor for current source which causes distortion is suppressed. Simulation results show the proposed Gm-cell can realize the same linearity as the conventional Gm-cell with reducing 36% power consumption. A 20MHz-bandwidth CT ΔΣ ADC employing the proposed Gm-cells achieves SNDR of 72.4dB with power consumption of 6.8mW. Active area and FoM of the ADC are, respectively, 250μm × 220μm and 50fJ/conv.-step in 65nm CMOS process.

A fully synthesizable all-digital phase-locked loop (AD-PLL) with a stochastic time-to-digital converter (STDC) is proposed in this paper. The whole AD-PLL circuit design is based on only standard cells from digital library, thus the layout of this AD-PLL can be automatically synthesized by a commercial place-and-route (P&R) tool with a foundry-provided standard-cell library. No manual layout and process modification is required in the whole AD-PLL design. In order to solve the delay mismatch issue in the delay-line-based time-to-digital converter (TDC), an STDC employing only standard D flip-flop (DFF) is presented to mitigate the sensitivity to layout mismatch resulted from automatic P&R. For the stochastic TDC, the key idea is to utilize the layout uncertainty due to automatic P&R which follows Gaussian distribution according to statistics theory. Moreover, the fully synthesized STDC can achieve a finer resolution compared to the conventional TDC. Implemented in a 28nm fully depleted silicon on insulator (FDSOI) technology, the fully synthesized PLL consumes only 480µW under 1.0V power supply while operating at 0.9GHz. It achieves a figure of merit (FoM) of -231.1dB with 4.0ps RMS jitter while occupying 0.0055mm2 chip area only.

This paper proposes a performance model for design of pipelined analog-to-digital converters (ADCs). This model includes the effect of overdrive voltage on the transistor, slewing of the operational amplifier, multi-bit structure of multiplying digital to analog converter (MDAC) and technology scaling. The conversion frequency of ADC is improved by choosing the optimum overdrive voltage of the transistor, an important consideration at smaller design rules. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. The performance model of pipelined ADC shown in this paper is attractive for the optimization of the ADC's performances.

We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital control blocks has been fabricated in a 0.18-µm CMOS process and consumes 118 µW at 1.8 V power supply. Also, the active area of ADC core is realized to be 0.027 mm2. The calibration improves the SNDR by 13.4 dB and the SFDR by 21.0 dB. The measured SNDR and SFDR at 1 kHz input are 55.2 dB and 73.2 dB respectively.

In order to realize highly accurate analog to digital conversion for EDTV, HDTV, and video-camera with low power consumption, a monolithic video-rate 8 bit parallel A/D converter has been developed using high-accuracy bipolar transistors with trench isolation. The A/D converter can digitize wide band video signals up to 10 MHz with high signal to nose ratio (45 dB at 10 MHz input) at high conversion rate of 40 MHz. Notwithstanding it contains 7000 bipolar transistors, it consumes only 250 mW and is formed with small chip size (2.73.9mm2).

A distribution of offset voltage of transistor pairs having fine pattern emitter down to 0.5 µm wide required for a parallel A/D converter can digitize at more than 200 MHz were measured. Moreover, contributions of transistor parameters to offset voltage and a realization of the ultra-high speed A/D converter were discussed. As the result, it was shown that the main transistor parameter contributes to the offset voltages is a fluctuation of a current gain, and a contribution of a emitter contact resistance was not so large. And the realization of 6 bit, 1 GHz or 8 bit, 750 MHz A/D converter was obtained.

This paper describes the analysis and design of low-noise analog circuits for a new architecture readout LSI, Qpix. In contrast to conventional readout LSIs using TOT method, Qpix measures deposited charge directly as well as time information. A preamplifier with a two-stage op amp and current-copy output buffers is proposed to realize these functions. This preamplifier is configured to implement a charge sensitive amplifier (CSA) and a trans-impedance amplifier (TIA). Design issues related to CSA are analyzed, which includes gain requirement of the op amp, stability and compensation of the two-stage cascode op amp, noise performance estimation, requirement for the resolution of the ADC and time response. The offset calibration method in the TIA to improve the charge detecting sensitivity is also presented. Also, some design principles for these analog circuits are presented. In order to verify the theoretical analysis, a 400-pixel high speed readout LSI: Qpix v.1 has been designed and fabricated in 180 nm CMOS process. Calculations and SPICE simulations show that the total output noise is about 0.31 mV (rms) at the output of the CSA and the offset voltage is less than 4 mV at the output of the TIA. These are attractive performances for experimental particle detector using Qpix v.1 chip as its readout LSI.

A 60-GHz CMOS transmitter with on-chip antenna for high-speed short-range wireless interconnections is presented. The radiation gain of the on-chip antenna is doubled using helium-3 ion irradiation technique. The transmitter core is composed of a resistive-feedback RF amplifier, a double-balanced passive mixer, and an injection-locked oscillator. The wideband and power-saving design of the transmitter core guarantees the low-power and high-data-rate characteristic. The transmitter fabricated in a 65-nm CMOS process achieves 5-Gb/s data rate with an EVM performance of $-$12 dB for BPSK modulation at a distance of 1,mm. The whole transmitter consumes 17,mW from a 1.2-V supply and occupies a core area of 0.64,mm$^{2}$ including the on-chip antenna. The gain-enhanced antenna together with the wideband and power-saving design of the transmitter provides a low-power low-cost full on-chip solution for the short-range high-data-rate wireless communication.

This paper presents a novel method of an on-sensor motion vector estimation. One of the key techniques is an iterative block matching algorithm using high-speed interpolated pictures. This technique allows us to estimate the video-rate (30 frame/s) motion vectors accurately from the motion vectors obtained at high-speed frames. The proposed iterative block matching reduces the computational complexity by a factor of more than one tenth compared to the conventional full search block matching algorithm. This property is particularly useful for the reduction of the power dissipation of video encoder. Another proposed technique is a high-speed non-destructive image sensing. This technique is essential to obtain high-speed interpolated pictures while maintaining high image quality in video-rate image sensing. The estimated power dissipation of the designed CMOS image sensor is sufficiently low, allowing us to achieve a totally low-power design of one-chip CMOS cameras integrating an image sensor and a video encoder.

An energy efficient modulator for an ultra-low-power (ULP) 60-GHz IEEE transmitter is presented in this paper. The modulator consists of a differential duobinary coder and a semi-digital finite-impulse-response (FIR) pulse-shaping filter. By virtue of differential duobinary coding and pulse shaping, the transceiver successfully solves the adjacent-channel-power-ratio (ACPR) issue of conventional on-off-keying (OOK) transceivers. The proposed differential duobinary code adopts an over-sampling precoder, which relaxes timing requirement and reduces power consumption. The semi-digital FIR eliminates the power hungry digital multipliers and accumulators, and improves the power efficiency through optimization of filter parameters. Fabricated in a 65nm CMOS process, this modulator occupies a core area of 0.12mm2. With a throughput of 1.7Gbps/2.6Gbps, power consumption of modulator is 24.3mW/42.8mW respectively, while satisfying the IEEE 802.11ad spectrum mask.

This paper describes a flash ADC using interpolation (IP) and cyclic background self-calibrating techniques. The proposed IP technique that is cascade of capacitor IP and gate IP with dynamic double-tail latched comparator reduces non-linearity, power consumption, and occupied area. The cyclic background self-calibrating technique periodically suppresses offset mismatch voltages caused by static fluctuation and dynamic fluctuation due to temperature and supply voltage changes. The ADC has been fabricated in 90-nm 1P10M CMOS technology. Experimental results show that the ADC achieves SNDR of 6.07 bits without calibration and 6.74 bits with calibration up to 500 MHz input signal at sampling rate of 600 MSps. It dissipates 98.5 mW on 1.2-V supply. FoM is 1.54 pJ/conv.

This paper presents the evaluation of the L-2L de-embedding method with misalignment of the contact position. The issues of misalignment of the contact position are investigated. The analysis of misalignment in the L-2L de-embedding procedure is performed. Two comparisons are carried out to verify the error of the L-2L de-embedding method. The calculation percent error in quality factor of the transmission line becomes up to 9.0%, while the transistor S-parameter error percentage becomes up to 21% at 60 GHz in the experimental results. The results show that the measurement errors, caused by the misalignment of the contact position, should be considered carefully.

A 6-bit, 7 mW, 700 MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90 nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, power dissipation and mismatch of conversion stages. By virtue of recent technology scaling, an interpolation can be realized in the saturation region with small error. A digital offset calibration technique using capacitor reduces comparator's offset voltage from 10 mV to 1.5 mV per sigma. Experimental results show that the proposed ADC achieves a SNDR of 34 dB with calibration and FoM is 250 fJ/conv., which is very attractive as an embedded IP for low power SoCs.

This paper describes a monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor Vbe matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within 0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of 59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0 4.2-mm2 chip integrating 36K elements, which consumes 4.0 W using a 1.0-µm-rule, 25-GHz ft, double-polysilicon self-aligned bipolar technology.

Negative feedback technique employing high DC gain operational amplifier (op-amp) is one of the most important techniques in analog circuit design. However, high DC gain op-amp is difficult to realize in scaled technology due to a decrease of intrinsic gain. In this paper, high DC gain op-amp using common-gate topology with high power efficiency is proposed. To achieve high DC gain, large output impedance is required but input transistors' drain conductance decreases output impedance of conventional topology such as folded cascode topology with complementary input. This is because bias current of the output side transistors is not separated from the bias current of the input transistors. On the other hand, proposed circuit can suppress a degradation of output impedance by inserting common-gate topology between input and output side. This architecture separates bias current of the input transistors from that of the output side, and hence the effect of the drain conductance of input transistors is reduced. As the result, proposed circuit can increase DC gain about 10,dB compared with the folded cascode topology with complementary input in 65,nm CMOS process. Moreover, power consumption can be reduced because input NMOS and PMOS share bias current. According to the simulation results, for the same power consumption, in the proposed circuit gain-bandwidth product (GBW) is improved by approximately 30% and noise is also reduced in comparison to the conventional topology.

This paper proposes an opamp-free solution to implement single-phase-clock controlled noise shaping in a SAR ADC. Unlike a conventional noise shaping SAR ADC, the proposal realizes noise shaping by charge redistribution, which is a passive technique. The passive implementation has high power efficiency. Meanwhile, since the proposal maintains the basic architecture and operation method of a traditional SAR ADC, it retains all the advantages of a SAR ADC. Furthermore, noise shaping helps to improve the performance of SAR ADC and relaxes its non-ideal effects. Designed in a 65-nm CMOS technology, the prototype realizes 58-dB SNDR based on an 8-bit C-DAC at 50-MS/s sampling frequency. It consumes 120.7-µW power from a 0.8-V supply and achieves a FoM of 14.8-fJ per conversion step.

A multi-port device is characterized using measurement results of a two-port Vector Network Analyzer (VNA) with four different structures. The loads used as terminations are open-, or short-circuited transmission lines (TLs), which are characterized along with Ground-Signal-Ground pads based on L-2L de-embedding method. A new characterization method for a four-port device is introduced along with its theory. The method is validated using simulation and measurement results. The characterized four-port device is a Crossing Transmission Line (CTL), mainly used for over-pass or under-pass of RF signals. Four measurement results are used to characterize the CTL. The S-parameter response of the CTL is found. To compare the results, reconstructed responses compared with the measurements. Results show good agreement between the measured and modeled results from 1 GHz to 110 GHz.

This paper proposes an ultra-low-voltage, wide signal swing, and clock-scalable differential dynamic amplifier using a common-mode voltage detection technique. The essential characteristics of an amplifier, such as gain, linearity, power consumption, noise, etc., are analyzed. In measurement, the proposed dynamic amplifier achieves a 13dB gain with less than 1dB drop over a differential output signal swing of 340mVpp with a supply voltage of 0.5V. The attained maximum operating frequency is 700MHz. With a 0.7V supply, the gain increases to 16dB with a signal swing of 700mVpp. The prototype amplifier is fabricated in 90nm CMOS technology with the low threshold voltage and the deep N-well options.

This paper presents a type-I digital ring-based PLL with wide loop bandwidth to lower the ring oscillator's noise contribution. The loop delay due to the D flip-flops at filter's output is compensated in order to lower the noise peak and stably achieve wide loop bandwidth. The input-referred jitter is lowered by using a successive-approximated-register analog-to-digital converter (SAR-ADC)-based sampling phase detector (SPD). A stacked reference buffer is introduced to reduce the transient short-circuit current for low power and low reference spur. The locking issue due to the steady-state phase error in a type-I PLL and the limited range of the phase detector is addressed using a TDC-assisted loop. The loop stability and phase noise are analyzed, suggesting a trade-off for the minimum jitter. The solutions in detail are described. The prototype PLL fabricated in 65 nm CMOS demonstrates 2.0 ps RMS jitter, 3.1 mW power consumption, and 0.067 mm2 area, with 50 MHz reference frequency and 2.0 GHz output frequency.

At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (Dgd) has been enlarged to obtain a better maximum available gain (MAG). By using the asymmetric-layout transistor, a 0.6 dB MAG improvement is realized when Dgd changes from 60 nm to 200 nm. A four-stage common-source low noise amplifier is implemented in a 65 nm CMOS process. A measured peak power gain of 24 dB is achieved with a power dissipation of 30 mW from a 1.2-V power supply. An 18 dB variable gain is also realized by adjusting the bias voltage. The measured 3-dB bandwidth is about 17 GHz from 51 GHz to 68 GHz, and noise figure (NF) is from 4.0 dB to 7.6 dB.