Design Challenges of Analog-to-Digital Converters in Nanoscale CMOS
Summary :
This paper discusses issues in the design of analog-to-digital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the low-voltage operation, the power consumption needs to be increased. Because of lowered supply voltages, the design of circuits based on operational amplifiers (OpAmps) has become more difficult. Designs without OpAmps have therefore received more attention. One way of realizing low-voltage pipeline ADCs is by using comparator-controlled current sources, instead of conventional OpAmps. Furthermore, successive approximation ADCs and sub-ranging ADCs do not require OpAmps and are therefore suitable for low-voltage operation. ADC designers are now searching for suitable architectures for future nanoscale CMOS processes.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.779-785
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.4.779
- Type of Manuscript
- Special Section INVITED PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
- Category
Authors
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Akira MATSUZAWA, "Design Challenges of Analog-to-Digital Converters in Nanoscale CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 4, pp. 779-785, April 2007, doi: 10.1093/ietele/e90-c.4.779.
Abstract: This paper discusses issues in the design of analog-to-digital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the low-voltage operation, the power consumption needs to be increased. Because of lowered supply voltages, the design of circuits based on operational amplifiers (OpAmps) has become more difficult. Designs without OpAmps have therefore received more attention. One way of realizing low-voltage pipeline ADCs is by using comparator-controlled current sources, instead of conventional OpAmps. Furthermore, successive approximation ADCs and sub-ranging ADCs do not require OpAmps and are therefore suitable for low-voltage operation. ADC designers are now searching for suitable architectures for future nanoscale CMOS processes.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.779/_p
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@ARTICLE{e90-c_4_779,
author={Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design Challenges of Analog-to-Digital Converters in Nanoscale CMOS},
year={2007},
volume={E90-C},
number={4},
pages={779-785},
abstract={This paper discusses issues in the design of analog-to-digital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the low-voltage operation, the power consumption needs to be increased. Because of lowered supply voltages, the design of circuits based on operational amplifiers (OpAmps) has become more difficult. Designs without OpAmps have therefore received more attention. One way of realizing low-voltage pipeline ADCs is by using comparator-controlled current sources, instead of conventional OpAmps. Furthermore, successive approximation ADCs and sub-ranging ADCs do not require OpAmps and are therefore suitable for low-voltage operation. ADC designers are now searching for suitable architectures for future nanoscale CMOS processes.},
keywords={},
doi={10.1093/ietele/e90-c.4.779},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Design Challenges of Analog-to-Digital Converters in Nanoscale CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 779
EP - 785
AU - Akira MATSUZAWA
PY - 2007
DO - 10.1093/ietele/e90-c.4.779
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - This paper discusses issues in the design of analog-to-digital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the low-voltage operation, the power consumption needs to be increased. Because of lowered supply voltages, the design of circuits based on operational amplifiers (OpAmps) has become more difficult. Designs without OpAmps have therefore received more attention. One way of realizing low-voltage pipeline ADCs is by using comparator-controlled current sources, instead of conventional OpAmps. Furthermore, successive approximation ADCs and sub-ranging ADCs do not require OpAmps and are therefore suitable for low-voltage operation. ADC designers are now searching for suitable architectures for future nanoscale CMOS processes.
ER -
English
