IEICE TRANSACTIONS on Electronics
A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS
Summary :
An energy efficient modulator for an ultra-low-power (ULP) 60-GHz IEEE transmitter is presented in this paper. The modulator consists of a differential duobinary coder and a semi-digital finite-impulse-response (FIR) pulse-shaping filter. By virtue of differential duobinary coding and pulse shaping, the transceiver successfully solves the adjacent-channel-power-ratio (ACPR) issue of conventional on-off-keying (OOK) transceivers. The proposed differential duobinary code adopts an over-sampling precoder, which relaxes timing requirement and reduces power consumption. The semi-digital FIR eliminates the power hungry digital multipliers and accumulators, and improves the power efficiency through optimization of filter parameters. Fabricated in a 65nm CMOS process, this modulator occupies a core area of 0.12mm2. With a throughput of 1.7Gbps/2.6Gbps, power consumption of modulator is 24.3mW/42.8mW respectively, while satisfying the IEEE 802.11ad spectrum mask.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E101-C No.2 pp.126-134
- Publication Date
- 2018/02/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E101.C.126
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Bangan LIU
Tokyo Institute of Technology
Yun WANG
Tokyo Institute of Technology
Jian PANG
Tokyo Institute of Technology
Haosheng ZHANG
Tokyo Institute of Technology
Dongsheng YANG
Tokyo Institute of Technology
Aravind Tharayil NARAYANAN
Tokyo Institute of Technology
Dae Young LEE
Samsung Electronics
Sung Tae CHOI
Samsung Electronics
Rui WU
Tokyo Institute of Technology
Kenichi OKADA
Tokyo Institute of Technology
Akira MATSUZAWA
Tokyo Institute of Technology
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Bangan LIU, Yun WANG, Jian PANG, Haosheng ZHANG, Dongsheng YANG, Aravind Tharayil NARAYANAN, Dae Young LEE, Sung Tae CHOI, Rui WU, Kenichi OKADA, Akira MATSUZAWA, "A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E101-C, no. 2, pp. 126-134, February 2018, doi: 10.1587/transele.E101.C.126.
Abstract: An energy efficient modulator for an ultra-low-power (ULP) 60-GHz IEEE transmitter is presented in this paper. The modulator consists of a differential duobinary coder and a semi-digital finite-impulse-response (FIR) pulse-shaping filter. By virtue of differential duobinary coding and pulse shaping, the transceiver successfully solves the adjacent-channel-power-ratio (ACPR) issue of conventional on-off-keying (OOK) transceivers. The proposed differential duobinary code adopts an over-sampling precoder, which relaxes timing requirement and reduces power consumption. The semi-digital FIR eliminates the power hungry digital multipliers and accumulators, and improves the power efficiency through optimization of filter parameters. Fabricated in a 65nm CMOS process, this modulator occupies a core area of 0.12mm2. With a throughput of 1.7Gbps/2.6Gbps, power consumption of modulator is 24.3mW/42.8mW respectively, while satisfying the IEEE 802.11ad spectrum mask.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E101.C.126/_p
Copy
@ARTICLE{e101-c_2_126,
author={Bangan LIU, Yun WANG, Jian PANG, Haosheng ZHANG, Dongsheng YANG, Aravind Tharayil NARAYANAN, Dae Young LEE, Sung Tae CHOI, Rui WU, Kenichi OKADA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS},
year={2018},
volume={E101-C},
number={2},
pages={126-134},
abstract={An energy efficient modulator for an ultra-low-power (ULP) 60-GHz IEEE transmitter is presented in this paper. The modulator consists of a differential duobinary coder and a semi-digital finite-impulse-response (FIR) pulse-shaping filter. By virtue of differential duobinary coding and pulse shaping, the transceiver successfully solves the adjacent-channel-power-ratio (ACPR) issue of conventional on-off-keying (OOK) transceivers. The proposed differential duobinary code adopts an over-sampling precoder, which relaxes timing requirement and reduces power consumption. The semi-digital FIR eliminates the power hungry digital multipliers and accumulators, and improves the power efficiency through optimization of filter parameters. Fabricated in a 65nm CMOS process, this modulator occupies a core area of 0.12mm2. With a throughput of 1.7Gbps/2.6Gbps, power consumption of modulator is 24.3mW/42.8mW respectively, while satisfying the IEEE 802.11ad spectrum mask.},
keywords={},
doi={10.1587/transele.E101.C.126},
ISSN={1745-1353},
month={February},}
Copy
TY - JOUR
TI - A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 126
EP - 134
AU - Bangan LIU
AU - Yun WANG
AU - Jian PANG
AU - Haosheng ZHANG
AU - Dongsheng YANG
AU - Aravind Tharayil NARAYANAN
AU - Dae Young LEE
AU - Sung Tae CHOI
AU - Rui WU
AU - Kenichi OKADA
AU - Akira MATSUZAWA
PY - 2018
DO - 10.1587/transele.E101.C.126
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E101-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2018
AB - An energy efficient modulator for an ultra-low-power (ULP) 60-GHz IEEE transmitter is presented in this paper. The modulator consists of a differential duobinary coder and a semi-digital finite-impulse-response (FIR) pulse-shaping filter. By virtue of differential duobinary coding and pulse shaping, the transceiver successfully solves the adjacent-channel-power-ratio (ACPR) issue of conventional on-off-keying (OOK) transceivers. The proposed differential duobinary code adopts an over-sampling precoder, which relaxes timing requirement and reduces power consumption. The semi-digital FIR eliminates the power hungry digital multipliers and accumulators, and improves the power efficiency through optimization of filter parameters. Fabricated in a 65nm CMOS process, this modulator occupies a core area of 0.12mm2. With a throughput of 1.7Gbps/2.6Gbps, power consumption of modulator is 24.3mW/42.8mW respectively, while satisfying the IEEE 802.11ad spectrum mask.
ER -
English
