An L-2L through-line de-embedding method has been verified up to millimeter wave frequency. The parasitics of the pad can be modeled from the L-2L through-line. Measurement results of the transmission lines and transistors can be de-embedded by subtracting the parasitic matrix of the pad. Therefore, the de-embedding patterns, which is used for modeling active and passive devices, decrease greatly and the chip area also decreases. A one-stage amplifier is firstly implemented for helping verifying the de-embedding results. After that a four-stage 60 GHz amplifier has been fabricated in CMOS 65 nm process. Experimental results show that the four-stage amplifier realizes an input matching better than -10.5 dB and an output matching better than -13 dB at 61 GHz. A small signal power gain of 16.4 dB and a 1 dB output compression point of 4.6 dBm are obtained with a DC current consumption of 128 mA from a 1.2 V power supply. The chip size is 1.5 mm 0.85 mm.

This paper concerns a new model for estimating the wire length distribution (WLD) of a system-on-a-chip (SoC). The WLD represents the correlation between wire length and the number of interconnects, and we can predict circuit performances such as power consumption, maximum clock frequency, and chip size from the WLD. A WLD model considering core utilization has been proposed, and the core utilization has a large impact on circuit performance. However, the WLD model can treat only a one-function circuit. We propose a new WLD model considering core utilization to estimate the wire length distribution of SoC, which consists of several different-function macroblocks. We present an optimization method to determine each core utilization of macroblocks.

This paper proposes a dual-conduction class-C VCO for ultra-low supply voltages. Two cross-coupled NMOS pairs with different bias points are employed. These NMOS pairs realize an impulse-like current waveform to improve the phase noise in the low supply conditions. The proposed VCO was implemented in a standard 0.18 µm CMOS technology, which oscillates at a carrier frequency of 4.5 GHz with a 0.2-V supply voltage. The measured phase noise is -104 dBc/Hz@1 MHz-offset with a power consumption of 114 µW, and the FoM is -187 dBc/Hz.

This paper proposes high-Q distributed constant passive devices using wafer-level chip scale package (WL-CSP) technology, which can be realized on a Si CMOS chip. A 90directional coupler using the WL-CSP technology has center frequency of 25.6 GHz, insertion loss of -0.5 dB and isolation of -29.8 dB in the measurement result. The WL-CSP technology contributes to realize low-loss RF passive devices on Si CMOS chip, which is indispensable to achieve small-size, cost-effective and low-power monolithic wireless communication circuits (MWCCs).

This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45nm SOI technology for validation. At an oscillation frequency of 5.0GHz, the proposed VCO achieves a phase noise of -120dBc/Hz at 1MHz offset, while consuming 1.35mW. This translates into an FoM of -191dBc/Hz.

This paper presents a high jitter performance injection-locked clock multiplier (ILCM) using an ultra-low power (ULP) voltage-controlled oscillator (VCO) for IoT application in 65-nm CMOS. The proposed transformer-based VCO achieves low flicker noise corner and sub-100µW power consumption. Double cross-coupled NMOS transistors sharing the same current provide high transconductance. The network using high-Q factor transformer (TF) provides a large tank impedance to minimize the current requirement. Thanks to the low current bias with a small conduction angle in the ULP VCO design, the proposed TF-based VCO's flicker noise can be suppressed, and a good PN can be achieved in flicker region (1/f3) with sub-100µW power consumption. Thus, a high figure-of-merit (FoM) can be obtained at both 100kHz and 1MHz without additional inductor. The proposed VCO achieves phase noise of -94.5/-115.3dBc/Hz at 100kHz/1MHz frequency offset with a 97µW power consumption, which corresponds to a -193/-194dBc/Hz VCO FoM at 2.62GHz oscillation frequency. The measurement results show that the 1/f3 corner is below 60kHz over the tuning range from 2.57GHz to 3.40GHz. Thanks to the proposed low power VCO, the total ILCM achieves 78 fs RMS jitter while using a high reference clock. A 960 fs RMS jitter can be achieved with a 40MHz common reference and 107µW corresponding power.

Analysis of resonance frequency in shorted transmission lines with inserted capacitor has been made. The analysis shows a resonance frequency dependence on capacitance position on a shorted transmission line. Two analysis methods are presented to predict the resonance frequency and understand how the inserted capacitor affects the resonance frequency of the shorted transmission line. Using this knowledge we propose a new structure for digital controlled oscillators utilizing the capacitance's sensitivity dependence on position of the shorted transmission line to increase the frequency resolution. A 9 GHz transmission line based digital controlled oscillator was designed and fabricated as a proof of concept. Measured results show that more than 100 times frequency step resolution increase is possible utilizing the same tuning capacitor size located at different points on the transmission line.

This paper introduces several design techniques to improve the performance of CMOS frequency multipliers that operate at the sub-THz band without increasing the complexity and the power consumption of the circuit. The proposed techniques are applied to a device nonlinearity-based frequency tripler and to a push-push frequency doubler. By utilizing the fundamental and second harmonic feedback cancellation, the tripler achieves -2.9dBm output power with a simple single-ended circuit architecture reducing the required area and power consumption. The tripler operates at frequencies from 103GHz to 130GHz. The introduced modified push-push doubler provides 2.3dB conversion gain including the balun losses and it has good tolerance against balun mismatches. The output frequency of the doubler is from 118GHz to 124GHz. Both circuits were designed and fabricated using CMOS 65nm technology.

This paper presents three CMOS power amplifiers (PA) which realize wide-tunable output impedance matching. For realization of multi-standard and single-chip transceiver, the prototypes were fabricated by 0.18 µm CMOS process. The proposed PAs can achieve a tunable impedance matching within a wide frequency range by utilizing a resistive feedback and parallel resonator with an inductor and capacitor array. Therefore, the proposed PA has a realization possibility of isolator-less PA which contributes to decrease die area including external component. In other words, the PAs have tunable impedance matching function at their output ends. With a 3.3-V supply, three power amplifiers can cover frequency ranges of 0.9–3.0 GHz, 2.1–5.8 GHz, and 5.7–9.7 GHz, respectively. The PAs realize P1 dB of 21 dBm, Psat of 22 dBm, and PAEpeak of larger than 23%. The proposed PAs present a potential to realize multi-band transceivers without isolators.

We propose a synthesis and automatic layout method for mixed-signal circuits with high regularity. As the first step of this research, a resistive digital-to-analog converter (RDAC) is presented. With a size calculation routine, the area of this RDAC is minimized while satisfying the required matching precision without any optimization loops. We propose to partition the design into slices comprising of both analog and digital cells. These cells are programmed to be synthesized as similar as custom P-Cells based on the calculation above, and automatically laid out to form one slice cell. To synthesize digital circuits, without using digital standard cell library, we propose a versatile unit digital block consisting of 8 transistors. With one or several blocks, the transistors' interconnections are programmed in the units to realize various logic gates. By using this block, the slice shapes are aligned so that the layout space in between the slices are minimized. The proposed mixed-signal slice-based partition facilitates the place-and-route of the whole RDAC. The post-layout simulation shows that the generated 9-bit RDAC achieves 1GHz sampling frequency, -0.11/0.09 and -0.30/0.75 DNL and INL, respectively, 3.57mW power consumption, and 0.0038mm2 active area.

This article presents a 28GHz high-accuracy phase and amplitude detection circuit for dual-polarized phased-array calibration. With dual-polarized calibration scheme, external LO signal is not required for calibration. The proposed detection circuit detects phase and amplitude independently, using PDC and ADC. By utilizing a 28GHz-to-140kHz downconversion scheme, the phase and amplitude are detected more accurately. In addition, reference signal for PDC and ADC is generated from 28GHz LO signal with divide-by-6 dual-step-mixing injection locked frequency divider (ILFD). This ILFD achieves 24.5-32.5GHz (28%) locking range with only 3.0mW power consumption and 0.01mm2 area. In the measurement, the detection circuit achieves phase and amplitude detections with RMS errors of 0.17degree and 0.12dB, respectively. The total power consumption of the proposed circuit is 59mW with 1-V supply voltage.

This paper presents two CMOS power amplifiers which realize frequency band selection. Each PA consists of two stages and uses a transformer to obtain large output power with high efficiency. Furthermore, the capacitive cross-coupling at the second stage reduces a die area of the bypass capacitance. The proposed PAs are fabricated by a 0.18 µm CMOS process. With a 3.3 V supply, the PAs achieve a output 1-dB compression point of larger than 25 dBm from 2.2 GHz to 5.4 GHz, maximum of peak power added efficiency (PAEpeak) are 30% and 27% for 2-band and 3-band PAs, respectively. The proposed PAs have advantages which are a band-selectable ability within a desired frequency range and a realization of CMOS PA with high power efficiency.

In this paper, a capacitive-cross-coupling common-gate (CCC-CG) LNA using capacitive feedback is proposed to improve the noise figure (NF). In the conventional CCC-CG LNA, the transconductance gm is determined by the input-matching condition while a lager gm is required to improve NF. gm of the proposed LNA can be increased and NF can be improved by using the added capacitive feedback. The analytical calculation shows that the proposed LNA can perform better than the conventional CCC-CG LNA. In the measurement results using a 0.18-µm CMOS technology, the gain is 10.4–13.4 dB, NF is 2.7–2.9 dB at 0.8–1.8 GHz, and IIP3 is -7 dBm at 0.8 GHz. The power consumption is 6.5 mW with a 1.8-V supply.

In this paper, we propose a via distribution model for yield estimation. This model expresses a relationship between the number of vias and wire length. We also provide an estimate for the total number of vias in a circuit, derived from the via distribution and the wire-length distribution. The via distribution is modeled as a function of track utilization, and the wire-length distribution can be derived from the gate-level netlist and the layout area. We extract model parameters from the commercial chips designed for 0.18-µm and 0.13-µm CMOS processes, and demonstrate the yield degradation caused by vias.

In this paper, we propose a new Interconnect Length Distribution (ILD) model to evaluate X architecture. X architecture uses 45-wire orientations in addition to 90-wire orientations, which contributes to reduce the total wire length and the number of vias. In this paper, we evaluated interconnect length distribution of diagonal (45orientations) and all-directional wiring. The average length and the longest length of interconnect are estimated, and 18% reduction in power consumption and 17% improvement in clock frequency can be obtained by the diagonal wiring in the experimental results. The all-directional wiring does not have large advantage as compared the diagonal wiring.

The present paper proposes differential transmission line structures on Si ULSI. Interconnect structures are examined using numerical results from a two-dimensional electromagnetic simulation (Ansoft, 2D Extractor). The co-planar and diagonal-pair lines are found to have superior characteristics for gigahertz signal propagation through long interconnects. The proposed diagonal-pair line can reduce the crosstalk noise and interconnect resource concurrently.

In this paper we present eigenmode analysis of the propagation constant for a microstrip line with dummy fills on a Si CMOS substrate. The effect of dummy fills is not negligible, particularly in the millimeter-wave band, although it has been ignored below frequencies of a few GHz. The propagation constant of a microstrip line with a periodic structure on a Si CMOS substrate is analyzed by eigenmode analysis for one period of the line. The calculated propagation constant and characteristic impedance were compared with measured values for a chip fabricated by the 0.18 µm CMOS process. The agreement between the analysis and measurement was very good. The dependence of loss on the arrangement of dummy fills was also investigated by eigenmode analysis. It was found that the transmission loss becomes large when dummy fills are arranged at places where the electromagnetic field is strong.

This paper present a 20-GHz differential push-push voltage controlled oscillator (VCO) for 60-GHz frequency synthesizer. The 20-GHz VCO consists of a 10-GHz in-phase injection-coupled QVCO (IPIC-QVCO) with tail-filter and a differential output push-push doubler for 20-GHz output. The VCO fabricated in 65-nm CMOS technology, it achieves tuning range of 3 GHz from 17.5 GHz to 20.4 GHz with a phase noise of -113.8 dBc/Hz at 1 MHz offset. The core oscillator consumes up to 71 mW power and a FoM of -180.2 dBc/Hz is achieved.

A fully synthesizable all-digital phase-locked loop (AD-PLL) with a stochastic time-to-digital converter (STDC) is proposed in this paper. The whole AD-PLL circuit design is based on only standard cells from digital library, thus the layout of this AD-PLL can be automatically synthesized by a commercial place-and-route (P&R) tool with a foundry-provided standard-cell library. No manual layout and process modification is required in the whole AD-PLL design. In order to solve the delay mismatch issue in the delay-line-based time-to-digital converter (TDC), an STDC employing only standard D flip-flop (DFF) is presented to mitigate the sensitivity to layout mismatch resulted from automatic P&R. For the stochastic TDC, the key idea is to utilize the layout uncertainty due to automatic P&R which follows Gaussian distribution according to statistics theory. Moreover, the fully synthesized STDC can achieve a finer resolution compared to the conventional TDC. Implemented in a 28nm fully depleted silicon on insulator (FDSOI) technology, the fully synthesized PLL consumes only 480µW under 1.0V power supply while operating at 0.9GHz. It achieves a figure of merit (FoM) of -231.1dB with 4.0ps RMS jitter while occupying 0.0055mm2 chip area only.