Wire Length Distribution Model for System LSI
Summary :
This paper concerns a new model for estimating the wire length distribution (WLD) of a system-on-a-chip (SoC). The WLD represents the correlation between wire length and the number of interconnects, and we can predict circuit performances such as power consumption, maximum clock frequency, and chip size from the WLD. A WLD model considering core utilization has been proposed, and the core utilization has a large impact on circuit performance. However, the WLD model can treat only a one-function circuit. We propose a new WLD model considering core utilization to estimate the wire length distribution of SoC, which consists of several different-function macroblocks. We present an optimization method to determine each core utilization of macroblocks.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.12 pp.3445-3452
- Publication Date
- 2005/12/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.12.3445
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Interconnect
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Takanori KYOGOKU, Junpei INOUE, Hidenari NAKASHIMA, Takumi UEZONO, Kenichi OKADA, Kazuya MASU, "Wire Length Distribution Model for System LSI" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 12, pp. 3445-3452, December 2005, doi: 10.1093/ietfec/e88-a.12.3445.
Abstract: This paper concerns a new model for estimating the wire length distribution (WLD) of a system-on-a-chip (SoC). The WLD represents the correlation between wire length and the number of interconnects, and we can predict circuit performances such as power consumption, maximum clock frequency, and chip size from the WLD. A WLD model considering core utilization has been proposed, and the core utilization has a large impact on circuit performance. However, the WLD model can treat only a one-function circuit. We propose a new WLD model considering core utilization to estimate the wire length distribution of SoC, which consists of several different-function macroblocks. We present an optimization method to determine each core utilization of macroblocks.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.12.3445/_p
Copy
@ARTICLE{e88-a_12_3445,
author={Takanori KYOGOKU, Junpei INOUE, Hidenari NAKASHIMA, Takumi UEZONO, Kenichi OKADA, Kazuya MASU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Wire Length Distribution Model for System LSI},
year={2005},
volume={E88-A},
number={12},
pages={3445-3452},
abstract={This paper concerns a new model for estimating the wire length distribution (WLD) of a system-on-a-chip (SoC). The WLD represents the correlation between wire length and the number of interconnects, and we can predict circuit performances such as power consumption, maximum clock frequency, and chip size from the WLD. A WLD model considering core utilization has been proposed, and the core utilization has a large impact on circuit performance. However, the WLD model can treat only a one-function circuit. We propose a new WLD model considering core utilization to estimate the wire length distribution of SoC, which consists of several different-function macroblocks. We present an optimization method to determine each core utilization of macroblocks.},
keywords={},
doi={10.1093/ietfec/e88-a.12.3445},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Wire Length Distribution Model for System LSI
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3445
EP - 3452
AU - Takanori KYOGOKU
AU - Junpei INOUE
AU - Hidenari NAKASHIMA
AU - Takumi UEZONO
AU - Kenichi OKADA
AU - Kazuya MASU
PY - 2005
DO - 10.1093/ietfec/e88-a.12.3445
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2005
AB - This paper concerns a new model for estimating the wire length distribution (WLD) of a system-on-a-chip (SoC). The WLD represents the correlation between wire length and the number of interconnects, and we can predict circuit performances such as power consumption, maximum clock frequency, and chip size from the WLD. A WLD model considering core utilization has been proposed, and the core utilization has a large impact on circuit performance. However, the WLD model can treat only a one-function circuit. We propose a new WLD model considering core utilization to estimate the wire length distribution of SoC, which consists of several different-function macroblocks. We present an optimization method to determine each core utilization of macroblocks.
ER -
English
