IEICE TRANSACTIONS on Fundamentals
Statistical Modeling of a Via Distribution for Yield Estimation
Summary :
In this paper, we propose a via distribution model for yield estimation. This model expresses a relationship between the number of vias and wire length. We also provide an estimate for the total number of vias in a circuit, derived from the via distribution and the wire-length distribution. The via distribution is modeled as a function of track utilization, and the wire-length distribution can be derived from the gate-level netlist and the layout area. We extract model parameters from the commercial chips designed for 0.18-µm and 0.13-µm CMOS processes, and demonstrate the yield degradation caused by vias.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.12 pp.3579-3584
- Publication Date
- 2006/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.12.3579
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Interconnect
Authors
Keyword
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Takumi UEZONO, Kenichi OKADA, Kazuya MASU, "Statistical Modeling of a Via Distribution for Yield Estimation" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 12, pp. 3579-3584, December 2006, doi: 10.1093/ietfec/e89-a.12.3579.
Abstract: In this paper, we propose a via distribution model for yield estimation. This model expresses a relationship between the number of vias and wire length. We also provide an estimate for the total number of vias in a circuit, derived from the via distribution and the wire-length distribution. The via distribution is modeled as a function of track utilization, and the wire-length distribution can be derived from the gate-level netlist and the layout area. We extract model parameters from the commercial chips designed for 0.18-µm and 0.13-µm CMOS processes, and demonstrate the yield degradation caused by vias.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.12.3579/_p
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@ARTICLE{e89-a_12_3579,
author={Takumi UEZONO, Kenichi OKADA, Kazuya MASU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Statistical Modeling of a Via Distribution for Yield Estimation},
year={2006},
volume={E89-A},
number={12},
pages={3579-3584},
abstract={In this paper, we propose a via distribution model for yield estimation. This model expresses a relationship between the number of vias and wire length. We also provide an estimate for the total number of vias in a circuit, derived from the via distribution and the wire-length distribution. The via distribution is modeled as a function of track utilization, and the wire-length distribution can be derived from the gate-level netlist and the layout area. We extract model parameters from the commercial chips designed for 0.18-µm and 0.13-µm CMOS processes, and demonstrate the yield degradation caused by vias.},
keywords={},
doi={10.1093/ietfec/e89-a.12.3579},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Statistical Modeling of a Via Distribution for Yield Estimation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3579
EP - 3584
AU - Takumi UEZONO
AU - Kenichi OKADA
AU - Kazuya MASU
PY - 2006
DO - 10.1093/ietfec/e89-a.12.3579
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2006
AB - In this paper, we propose a via distribution model for yield estimation. This model expresses a relationship between the number of vias and wire length. We also provide an estimate for the total number of vias in a circuit, derived from the via distribution and the wire-length distribution. The via distribution is modeled as a function of track utilization, and the wire-length distribution can be derived from the gate-level netlist and the layout area. We extract model parameters from the commercial chips designed for 0.18-µm and 0.13-µm CMOS processes, and demonstrate the yield degradation caused by vias.
ER -
English
