This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45nm SOI technology for validation. At an oscillation frequency of 5.0GHz, the proposed VCO achieves a phase noise of -120dBc/Hz at 1MHz offset, while consuming 1.35mW. This translates into an FoM of -191dBc/Hz.

A fully synthesizable all-digital phase-locked loop (AD-PLL) with a stochastic time-to-digital converter (STDC) is proposed in this paper. The whole AD-PLL circuit design is based on only standard cells from digital library, thus the layout of this AD-PLL can be automatically synthesized by a commercial place-and-route (P&R) tool with a foundry-provided standard-cell library. No manual layout and process modification is required in the whole AD-PLL design. In order to solve the delay mismatch issue in the delay-line-based time-to-digital converter (TDC), an STDC employing only standard D flip-flop (DFF) is presented to mitigate the sensitivity to layout mismatch resulted from automatic P&R. For the stochastic TDC, the key idea is to utilize the layout uncertainty due to automatic P&R which follows Gaussian distribution according to statistics theory. Moreover, the fully synthesized STDC can achieve a finer resolution compared to the conventional TDC. Implemented in a 28nm fully depleted silicon on insulator (FDSOI) technology, the fully synthesized PLL consumes only 480µW under 1.0V power supply while operating at 0.9GHz. It achieves a figure of merit (FoM) of -231.1dB with 4.0ps RMS jitter while occupying 0.0055mm2 chip area only.

An energy efficient modulator for an ultra-low-power (ULP) 60-GHz IEEE transmitter is presented in this paper. The modulator consists of a differential duobinary coder and a semi-digital finite-impulse-response (FIR) pulse-shaping filter. By virtue of differential duobinary coding and pulse shaping, the transceiver successfully solves the adjacent-channel-power-ratio (ACPR) issue of conventional on-off-keying (OOK) transceivers. The proposed differential duobinary code adopts an over-sampling precoder, which relaxes timing requirement and reduces power consumption. The semi-digital FIR eliminates the power hungry digital multipliers and accumulators, and improves the power efficiency through optimization of filter parameters. Fabricated in a 65nm CMOS process, this modulator occupies a core area of 0.12mm2. With a throughput of 1.7Gbps/2.6Gbps, power consumption of modulator is 24.3mW/42.8mW respectively, while satisfying the IEEE 802.11ad spectrum mask.

This paper proposes a pulse-tail-feedback VCO, in which the tail transistor is driven using pulse-shaped voltage signals with rail-to-rail swing. The proposed pulse-tail-feedback (PTFB) VCO relies on reducing the current conduction period of the tail transistor and operating the tail transistors in triode region for reducing the flicker and thermal noise from the active elements. Mathematical analysis and circuit level simulations of the phase noise mechanism in the proposed PTFB-VCO is also presented in this paper for validating the effectiveness of the proposed technique. A prototype LC-VCO with the proposed PTFB technique is fabricated in a standard 180nm CMOS. Laboratory measurement shows a power consumption of 1.35mW from a 1.2V supply at 4.6GHz. The proposed PTFB-VCO achieves a flicker corner of 700Hz, which enables the VCO to maintain a fairly constant figure-of-merit (FoM) of -195dB within a wide offset frequency range of 1kHz-10MHz.

This paper presents a 20GHz Class-C VCO using a noise sensitivity mitigation technique. A radio frequency Class-C VCO suffers from the AM-PM conversion, caused by the non-linear capacitance of cross coupled pair. In this paper, the phase noise degradation mechanism is discussed, and a desensitization technique of AM-PM noise is proposed. In the proposed technique, AM-PM sensitivity is canceled by tuning the tail impedance, which consists of 4-bit resistor switches. A 65-nm CMOS prototype of the proposed VCO demonstrates the oscillation frequency from 19.27 to 22.4GHz, and the phase noise of -105.7dBc/Hz at 1-MHz offset with the power dissipation of 6.84mW, which is equivalent to a Figure-of-Merit of -183.73dBc/Hz.

An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. The system achieves a maximum data rate of 10.06Gbps while consuming a power of 16.1mW from a 1V power supply.