This paper presents a fully integrated yet compact receiver front-end for Sub-GHz applications such as Internet-of-Things (IoT). The low noise amplifier (LNA) matching network leverages an inductance boosting technique. A relatively small on-chip inductor with a compact area achieves impedance matching in such a low frequency. Moreover, a passive-mixer-first mode bypasses the LNA to extend the receiver dynamic-range. The passive mixer provides matching to the 50Ω antenna interface to eliminate the need for additional passive components. Therefore, the receiver can be fully-integrated without any off-chip matching components. The flipped-voltage-follower (FVF) cell is adopted in the low pass filter (LPF) and the variable gain amplifier (VGA) for its high linearity and low power consumption. Fabricated in 65nm LP CMOS process, the proposed receiver front-end occupies 0.37mm2 core area, with a tolerable input power ranging from -91.5dBm to -1dBm for 500kbps GMSK signal at 924MHz frequency. The power consumption is 1mW power under a 1.2V supply.

Regarding the enlarged array size for the 5G new radio (NR) millimeter-wave phased-array transceivers, an improved phase tuning resolution will be required to support the accurate beam control. This paper introduces a CMOS implementation of an active vector-summing phase shifter. The proposed phase shifter realizes a 6-bit phase shifting with an active area of 0.32mm2. To minimize the gain variation during the phase tuning, a gain error compensation technique is proposed. After the compensation, the measured gain variation within the 5G NR band n257 is less than 0.9dB. The corresponding RMS gain error is less than 0.2dB. The measured RMS phase error from 26.5GHz to 29.5GHz is less than 1.2°. Gain-invariant, high-resolution phase tuning is realized by this work. Considering the error vector magnitude (EVM) performance, the proposed phase shifter supports a maximum data rate of 11.2Gb/s in 256QAM with a power consumption of 25.2mW.

This paper presents a high-resolution and low-insertion-loss CMOS hybrid phase shifter with a nonuniform matching technique for satellite communication (SATCOM). The proposed hybrid phase shifter includes three 45° coarse phase-shifting stages and one 45° fine phase-tuning stage. The coarse stages are realized by bridged-T switch-type phase shifters (STPS) with 45° phase steps. The fine-tuning stage is based on a reflective-type phase shifter (RTPS) with two identical LC load tanks for phase tuning. A 0.8° phase resolution is realized by this work to support fine beam steering for the SATCOM. To further reduce the chain insertion loss, a nonuniform matching technique is utilized at the coarse stages. For the coarse and fine stages, the measured RMS gain errors at 29GHz are 0.7dB and 0.3dB, respectively. The measured RMS phase errors are 0.8° and 0.4°, respectively. The proposed hybrid phase shifter maintains return losses of all phase states less than -12dB from 24GHz to 34GHz. The presented hybrid phase shifter is fabricated in a standard 65-nm CMOS technology with a 0.14mm2 active area.

This paper presents a miniaturized transformer-based ultra-low-power (ULP) LC-VCO with embedded supply pushing reduction techniques for IoT applications in 65-nm CMOS process. To reduce the on-chip area, a compact transformer patterned ground shield (PGS) is implemented. The transistors with switchable capacitor banks and associated components are placed underneath the transformer, which further shrinking the on-chip area. To lower the power consumption of VCO, a gm-stacked LC-VCO using the transformer embedded with PGS is proposed. The transformer is designed to provide large inductance to obtain a robust start-up within limited power consumption. Avoiding implementing an off/on-chip Low-dropout regulator (LDO) which requires additional voltage headroom, a low-power supply pushing reduction feedback loop is integrated to mitigate the current variation and thus the oscillation amplitude and frequency can be stabilized. The proposed ULP TF-based LC-VCO achieves phase noise of -114.8dBc/Hz at 1MHz frequency offset and 16kHz flicker corner with a 103µW power consumption at 2.6GHz oscillation frequency, which corresponds to a -193dBc/Hz VCO figure-of-merit (FoM) and only occupies 0.12mm2 on-chip area. The supply pushing is reduced to 2MHz/V resulting in a -50dBc spur, while 5MHz sinusoidal ripples with 50mVPP are added on the DC supply.

This paper introduces a high-resolution and compact CMOS switch-type phase shifter (STPS) for the 5th generation mobile network (5G) n260 band. In this work, totally four coarse phase shifting stages and a high-resolution tuning stage are included. The coarse stages based on the bridged-T topology is capable of providing 202.5° phase coverage with a 22.5° tuning step. To further improve the phase shifting resolution, a compact fine-tuning stage covering 23° is also integrated with the coarse stages. Sub-degree phase shifting resolution is realized for supporting the fine beam-steering and high-accuracy phase calibration in the 5G new radio. Simplified phase control algorithm and suppressed insertion loss can also be maintained by the proposed fine-tuning stage. In the measurement, the achieved RMS gain errors at 39 GHz are 0.1 dB and 0.4 dB for the coarse stages and fine stage, respectively. The achieved RMS phase errors at 39 GHz are 3.1° for the coarse stages and 0.1° for the fine stage. Within 37 GHz to 40 GHz, the measured return loss within all phase-tuning states is always better than -14 dB. The proposed phase shifter consumes a core area of only 0.12mm2 with 65-nm CMOS process, which is area-efficient.

This paper presents a physical layer wireless device identification method that uses a convolutional neural network (CNN) operating on a quadrant IQ transition image. This work introduces classification and detection tasks in one process. The proposed method can identify IoT wireless devices by exploiting their RF fingerprints, a technology to identify wireless devices by using unique variations in analog signals. We propose a quadrant IQ image technique to reduce the size of CNN while maintaining accuracy. The CNN utilizes the IQ transition image, which image processing cut out into four-part. An over-the-air experiment is performed on six Zigbee wireless devices to confirm the proposed identification method's validity. The measurement results demonstrate that the proposed method can achieve 99% accuracy with the light-weight CNN model with 36,500 weight parameters in serial use and 146,000 in parallel use. Furthermore, the proposed threshold algorithm can verify the authenticity using one classifier and achieved 80% accuracy for further secured wireless communication. This work also introduces the identification of expanded signals with SNR between 10 to 30dB. As a result, at SNR values above 20dB, the proposals achieve classification and detection accuracies of 87% and 80%, respectively.

There are enlarged requirements of millimeter-wave beamforming phased-array transceivers and high-order modulation multi-input multi-output (MIMO) transceivers. High-performance integrated RF switches are regarded as one of the most critical components for those transceivers to support signal channel distribution and path redundancy. This paper introduces a CMOS high-isolation and low-loss RF switch with a novel switched parallel LC resonance network. The proposed single-pole double-throw (SPDT) RF switch realizes 68dB port isolation and 1.0dB insertion loss with an active area of 0.034mm2. The SPDT RF switch is composed of two series-shunt transistor pairs with body-floating technology and a switched parallel LC network. The network uses a turned-off series transistor to resonate out off-capacitance Coff. The measured output third-order intercept (OIP3) is higher than 21dBm. The proposed SPDT RF switch maintains return losses of all working ports less than 10dB from 8GHz to 20GHz. The high-performance SPDT RF switch is fabricated in standard 65-nm CMOS technology.

This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45nm SOI technology for validation. At an oscillation frequency of 5.0GHz, the proposed VCO achieves a phase noise of -120dBc/Hz at 1MHz offset, while consuming 1.35mW. This translates into an FoM of -191dBc/Hz.

This paper presents a high jitter performance injection-locked clock multiplier (ILCM) using an ultra-low power (ULP) voltage-controlled oscillator (VCO) for IoT application in 65-nm CMOS. The proposed transformer-based VCO achieves low flicker noise corner and sub-100µW power consumption. Double cross-coupled NMOS transistors sharing the same current provide high transconductance. The network using high-Q factor transformer (TF) provides a large tank impedance to minimize the current requirement. Thanks to the low current bias with a small conduction angle in the ULP VCO design, the proposed TF-based VCO's flicker noise can be suppressed, and a good PN can be achieved in flicker region (1/f3) with sub-100µW power consumption. Thus, a high figure-of-merit (FoM) can be obtained at both 100kHz and 1MHz without additional inductor. The proposed VCO achieves phase noise of -94.5/-115.3dBc/Hz at 100kHz/1MHz frequency offset with a 97µW power consumption, which corresponds to a -193/-194dBc/Hz VCO FoM at 2.62GHz oscillation frequency. The measurement results show that the 1/f3 corner is below 60kHz over the tuning range from 2.57GHz to 3.40GHz. Thanks to the proposed low power VCO, the total ILCM achieves 78 fs RMS jitter while using a high reference clock. A 960 fs RMS jitter can be achieved with a 40MHz common reference and 107µW corresponding power.

This paper introduces several design techniques to improve the performance of CMOS frequency multipliers that operate at the sub-THz band without increasing the complexity and the power consumption of the circuit. The proposed techniques are applied to a device nonlinearity-based frequency tripler and to a push-push frequency doubler. By utilizing the fundamental and second harmonic feedback cancellation, the tripler achieves -2.9dBm output power with a simple single-ended circuit architecture reducing the required area and power consumption. The tripler operates at frequencies from 103GHz to 130GHz. The introduced modified push-push doubler provides 2.3dB conversion gain including the balun losses and it has good tolerance against balun mismatches. The output frequency of the doubler is from 118GHz to 124GHz. Both circuits were designed and fabricated using CMOS 65nm technology.

This article presents a 28GHz high-accuracy phase and amplitude detection circuit for dual-polarized phased-array calibration. With dual-polarized calibration scheme, external LO signal is not required for calibration. The proposed detection circuit detects phase and amplitude independently, using PDC and ADC. By utilizing a 28GHz-to-140kHz downconversion scheme, the phase and amplitude are detected more accurately. In addition, reference signal for PDC and ADC is generated from 28GHz LO signal with divide-by-6 dual-step-mixing injection locked frequency divider (ILFD). This ILFD achieves 24.5-32.5GHz (28%) locking range with only 3.0mW power consumption and 0.01mm2 area. In the measurement, the detection circuit achieves phase and amplitude detections with RMS errors of 0.17degree and 0.12dB, respectively. The total power consumption of the proposed circuit is 59mW with 1-V supply voltage.