IEICE TRANSACTIONS on Electronics
A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock
Summary :
This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45nm SOI technology for validation. At an oscillation frequency of 5.0GHz, the proposed VCO achieves a phase noise of -120dBc/Hz at 1MHz offset, while consuming 1.35mW. This translates into an FoM of -191dBc/Hz.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E102-C No.4 pp.276-286
- Publication Date
- 2019/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2018CDP0010
- Type of Manuscript
- Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
- Category
Authors
Haosheng ZHANG
Tokyo Institute of Technology
Aravind THARAYIL NARAYANAN
Tokyo Institute of Technology
Hans HERDIAN
Tokyo Institute of Technology
Bangan LIU
Tokyo Institute of Technology
Rui WU
Tokyo Institute of Technology
Atsushi SHIRANE
Tokyo Institute of Technology
Kenichi OKADA
Tokyo Institute of Technology
Keyword
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Haosheng ZHANG, Aravind THARAYIL NARAYANAN, Hans HERDIAN, Bangan LIU, Rui WU, Atsushi SHIRANE, Kenichi OKADA, "A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock" in IEICE TRANSACTIONS on Electronics,
vol. E102-C, no. 4, pp. 276-286, April 2019, doi: 10.1587/transele.2018CDP0010.
Abstract: This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45nm SOI technology for validation. At an oscillation frequency of 5.0GHz, the proposed VCO achieves a phase noise of -120dBc/Hz at 1MHz offset, while consuming 1.35mW. This translates into an FoM of -191dBc/Hz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2018CDP0010/_p
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@ARTICLE{e102-c_4_276,
author={Haosheng ZHANG, Aravind THARAYIL NARAYANAN, Hans HERDIAN, Bangan LIU, Rui WU, Atsushi SHIRANE, Kenichi OKADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock},
year={2019},
volume={E102-C},
number={4},
pages={276-286},
abstract={This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45nm SOI technology for validation. At an oscillation frequency of 5.0GHz, the proposed VCO achieves a phase noise of -120dBc/Hz at 1MHz offset, while consuming 1.35mW. This translates into an FoM of -191dBc/Hz.},
keywords={},
doi={10.1587/transele.2018CDP0010},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock
T2 - IEICE TRANSACTIONS on Electronics
SP - 276
EP - 286
AU - Haosheng ZHANG
AU - Aravind THARAYIL NARAYANAN
AU - Hans HERDIAN
AU - Bangan LIU
AU - Rui WU
AU - Atsushi SHIRANE
AU - Kenichi OKADA
PY - 2019
DO - 10.1587/transele.2018CDP0010
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2019
AB - This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45nm SOI technology for validation. At an oscillation frequency of 5.0GHz, the proposed VCO achieves a phase noise of -120dBc/Hz at 1MHz offset, while consuming 1.35mW. This translates into an FoM of -191dBc/Hz.
ER -
English
