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A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock

Haosheng ZHANG, Aravind THARAYIL NARAYANAN, Hans HERDIAN, Bangan LIU, Rui WU, Atsushi SHIRANE, Kenichi OKADA

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Summary :

This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45nm SOI technology for validation. At an oscillation frequency of 5.0GHz, the proposed VCO achieves a phase noise of -120dBc/Hz at 1MHz offset, while consuming 1.35mW. This translates into an FoM of -191dBc/Hz.

Publication
IEICE TRANSACTIONS on Electronics Vol.E102-C No.4 pp.276-286
Publication Date
2019/04/01
Publicized
Online ISSN
1745-1353
DOI
10.1587/transele.2018CDP0010
Type of Manuscript
Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category

Authors

Haosheng ZHANG
  Tokyo Institute of Technology
Aravind THARAYIL NARAYANAN
  Tokyo Institute of Technology
Hans HERDIAN
  Tokyo Institute of Technology
Bangan LIU
  Tokyo Institute of Technology
Rui WU
  Tokyo Institute of Technology
Atsushi SHIRANE
  Tokyo Institute of Technology
Kenichi OKADA
  Tokyo Institute of Technology

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