Precision microwave measurement systems require highly stable oscillators with both excellent long-term and short-term stability. Compared to components used in laboratory instruments, dielectric resonator oscillators (DRO) offer low phase noise with greatly reduced mechanical complexity. To further enhance performance, phase-locked loop (PLL) stabilization can be used to eliminate drift and provide precise frequency control. In this work, the design of a low-cost DRO concept is presented and its performance is evaluated through simulations and measurements. An open-loop phase noise of -107.2 dBc/Hz at 10 kHz offset frequency and 12.8 GHz output frequency is demonstrated. Drift and phase noise are reduced by a PLL, so that a very low jitter of under 29.6 fs is achieved over the entire operating bandwidth.

In this paper, we propose a hybrid crystal oscillator which achieves both quick startup and low steady-state power consumption. At startup, a large negative resistance is realized by configuring a Pierce oscillating circuit with a multi-stage inverter amplifier, resulting in high-speed startup. During steady-state oscillation, the oscillator is reconfigured as a class-C complementary Colpitts circuit for low power consumption and low phase noise. Prototype chips were fabricated in 65nm CMOS process technology. With Pierce-type configuration, the measured startup time and startup energy of the oscillator are reduced to 1/11 and 1/5, respectively, compared with the one without Pierce-type configuration. The power consumption during steady oscillation is 30 µW.

Quadrature voltage-controlled oscillators (VCOs) with current-weight-average and voltage-weight-average phase-adjusting architectures are studied. The phase adjusting equalizes the oscillation frequency to the LC-resonant frequency. The merits of the equalization are explained by using Leeson's phase noise equation and the impulse sensitivity function (ISF). Quadrature VCOs with the phase-adjusting architectures are fabricated using 180-nm TSMC CMOS and show low-phase-noise performances compared to a conventional differential VCO. The ISF analysis and small-signal analysis also show that the drawbacks of the current-weight-average phase-adjusting and voltage-weight-average phase-adjusting architectures are current-source noise effect and large additional capacitance, respectively. A voltage-average-adjusting circuit with a source follower at its input alleviates the capacitance increase.

A hard-type oscillator is defined as an oscillator having stable fixed points within a stable limit cycle. For resonant tunneling diode (RTD) oscillators, using hard-type configuration has a significant advantage that it can suppress spurious oscillations in a bias line. We have fabricated hard-type oscillators using an InGaAs-based RTD, and demonstrated a proper operation. Furthermore, the oscillating properties have been compared with a soft-type oscillator having a same parameters. It has been demonstrated that the same level of the phase noise can be obtained with a much smaller power consumption of approximately 1/20.

In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.

Frequency delta sigma modulation (FDSM) is a unique analog to digital conversion technique featuring large dynamic range with wide frequency band width. It can be used for high performance digital-output sensors, if the oscillator in the FDSM is replaced by a variable frequency oscillator whose frequency depends on a certain external physical quantity. One of the most important parameters governing the performance of these sensors is a phase noise of the oscillator. The phase noise is an essential error source in the FDSM, and it is quite important for this type of sensors because they use a high frequency oscillator and an extremely large oversampling ratio. In this paper, we will discuss the quantitative effects of the phase noise on the FDSM output on the basis of a simple model. The model was validated with experiments for three types of oscillators.

This paper proposes a pulse-tail-feedback VCO, in which the tail transistor is driven using pulse-shaped voltage signals with rail-to-rail swing. The proposed pulse-tail-feedback (PTFB) VCO relies on reducing the current conduction period of the tail transistor and operating the tail transistors in triode region for reducing the flicker and thermal noise from the active elements. Mathematical analysis and circuit level simulations of the phase noise mechanism in the proposed PTFB-VCO is also presented in this paper for validating the effectiveness of the proposed technique. A prototype LC-VCO with the proposed PTFB technique is fabricated in a standard 180nm CMOS. Laboratory measurement shows a power consumption of 1.35mW from a 1.2V supply at 4.6GHz. The proposed PTFB-VCO achieves a flicker corner of 700Hz, which enables the VCO to maintain a fairly constant figure-of-merit (FoM) of -195dB within a wide offset frequency range of 1kHz-10MHz.

This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45nm SOI technology for validation. At an oscillation frequency of 5.0GHz, the proposed VCO achieves a phase noise of -120dBc/Hz at 1MHz offset, while consuming 1.35mW. This translates into an FoM of -191dBc/Hz.

This paper describes a broadband low phase noise VCO implemented in 0.13 µm CMOS process. A 1-bit switched varactor and a 4-bit capacitor array are adopted in cooperation with the automatic frequency calibration (AFC) circuit to lower the VCO tuning gain (KVCO), with a measured AFC time of 6 µs. Several noise reduction techniques are exploited to minimize the phase noise of the VCO. Measurement results show the VCO generates a high frequency range from 11.37 GHz to 14.8 GHz with a KVCO of less than 270 MHz/V. The prototype exhibits a phase noise of -114.6 dBc/Hz @ 1 MHz at 14.67 GHz carrier frequency and draws 10.5 mA current from a 1.2 V supply. The achieved figure-of-merits (FoM=-186.9dBc/Hz, FoMT=-195.3dBc/Hz) favorably compares with the state-of-the-art.

This paper describes a novel composite right-/left-handed (CRLH) transmission line (TL) stub resonator for X-band low phase-noise oscillator application. The bandpass filter type resonator composed only of microstrip components exhibits unloaded-Q exceeding that of microstrip-line resonators by engineering the dispersion relation for the CRLH TL. Two different types of stub resonator using identical and non-identical unit-cells are compared. Although the latter type was found to be superior to the former in terms of spurious frequency responses and the circuit size, care was taken to prevent the parasitic inductances distributed in the interdigital capacitors from impeding the Q-factor control capability of the resonator. The stub resonator thus optimized was applied to an 8.8-GHz SiGe HBT oscillator, which achieved a phase-noise of -134dBc/Hz at 1-MHz offset despite the modest dielectric loss tangent of the PCB laminate used as the substrate of the circuit.

This paper presents a 27.5-29.6GHz fractional-N frequency synthesizer using reference and frequency doublers to achieve low in-band and out-of-band phase-noise for 5G mobile communications. A consideration of the baseband carrier recovery circuit helps estimate phase noise requirement for high modulation scheme. The push-push amplifier and 28GHz balun help achieving differential signals with low out-of-band phase noise while consuming low power. A charge pump with gated offset as well as reference doubler help reducing PD noise resulting in low in-band phase noise while sampling loop filter helps reduce spurs. The proposed synthesizer has been implemented in 65nm CMOS technology achieving an in-band and out-of-band phase noise of -78dBc/Hz and -126dBc/Hz, respectively. It consumes only a total power of 33mW. The jitter-power figure-of-merit (FOM) is -231dB which is the highest among the state of the art >20GHz fractional-N PLLs using a low reference clock (<200MHz). The measured reference spurs are less than -80dBc.

This paper proposes approximated log likelihood ratios (LLRs) for single carrier millimeter-wave (mmW) transmission systems in the presence of phase noise. In mmW systems, phase noise on carrier wave signals in very high frequency bands causes severe performance degradation. In order to mitigate the impairments of phase noise, forward error correction (FEC) techniques, such as low density parity check (LDPC) code, are effective. However, if the probabilistic model does not capture the exact behavior of the random process present in the received signal, FEC performance is severely degraded, especially in higher order modulation or high coding rate cases. To address this issue, we carefully examine the probabilistic model of minimum mean square error (MMSE) equalizer output including phase noise component. Based on the derived probabilistic model, approximated LLR computation methods with low computational burden are proposed. Computer simulations confirm that the approximated LLR computations on the basis of the derived probabilistic model are capable of improving bit error rate (BER) performance without sacrificing computational simplicity in the presence of phase noise.

This paper present a 20-GHz differential push-push voltage controlled oscillator (VCO) for 60-GHz frequency synthesizer. The 20-GHz VCO consists of a 10-GHz in-phase injection-coupled QVCO (IPIC-QVCO) with tail-filter and a differential output push-push doubler for 20-GHz output. The VCO fabricated in 65-nm CMOS technology, it achieves tuning range of 3 GHz from 17.5 GHz to 20.4 GHz with a phase noise of -113.8 dBc/Hz at 1 MHz offset. The core oscillator consumes up to 71 mW power and a FoM of -180.2 dBc/Hz is achieved.

This paper studies a novel iterative detection algorithm for data detection in orthogonal frequency division multiplexing systems in the presence of phase noise (PHN) and channel estimation errors. By simplifying the maximum a posteriori algorithm based on the theory of variational inference, an optimization problem over variational free energy is formulated. After that, the estimation of data, PHN and channel state information is obtained jointly and iteratively. The simulations indicate the validity of this algorithm and show a better performance compared with the traditional schemes.

A 1.9GHz film bulk acoustic resonator (FBAR)-based low-phase-noise complementary cross-coupled voltage-controlled oscillator (VCO) is presented. The FBAR-VCO is designed and fabricated in 0.18µm CMOS process. The DC latch and the low frequency instability are resolved by employing the NMOS source coupling capacitor and the DC blocked cross-coupled pairs. Since no additional voltage headroom is required, the proposed FBAR-VCO can be operated at a low power supply voltage of 1.1V with a wide voltage swing of 0.9V. An effective phase noise optimization is realized by a reasonable trade-off between the output resistance and the trans-conductance of the cross-coupled pairs. The measured performance shows the proposed FBAR-VCO achieves a phase noise of -148dBc/Hz at 1MHz offset with a figure of merit (FoM) of -211.6dB.

A novel optical high order quadrature amplitude modulation (QAM) transmission system for high-speed short links is described. Dual-polarization (DP) QAM and twin local lights are generated from one light source in the system, and these lightwaves are simultaneously transmitted via standard single mode fiber. The receiver can be constructed simply because it does not require a coherent light source under wavelength control. The system enables a 3.1 Gbaud DP-16-QAM signal to be successfully demodulated after 80-km transmission without using an optical dispersion compensator. It also achieves high tolerance against phase noise in the signal light source.

We present a design method for miniaturizing double stub resonators that are potentially very useful for wide range of applications but have limited usage for MMICs due to their large footprint. The analytical design model, which we introduce in this paper, allows for determining the capacitances needed to achieve the targeted shrinking ratio while maintaining the original loaded-Q before miniaturization. To verify the model, 18-GHz stub resonators that are around 40% of the original sizes were designed and fabricated in GaAs MMIC technology. The effectiveness of the proposed technique is also demonstrated by a 9-GHz low phase-noise oscillator using the miniaturized resonator.

Synthetic aperture radar (SAR) imagery is significantly deteriorated by the random phase noises which are generated by the frequency jitter of the transmit signal and atmospheric turbulence. In this paper, we recast the SAR imaging problem via the phase-corrupted data as for a special case of quadratic compressed sensing (QCS). Although the quadratic measurement model has potential to mitigate the effects of the phase noises, it also leads to a nonconvex and quartic optimization problem. In order to overcome these challenges and increase reconstruction robustness to the phase noises, we proposed a QCS-based SAR imaging algorithm by greedy local search to exploit the spatial sparsity of scatterers. Our proposed imaging algorithm can not only avoid the process of precise random phase noise estimation but also acquire a sparse representation of the SAR target with high accuracy from the phase-corrupted data. Experiments are conducted by the synthetic scene and the moving and stationary target recognition Sandia laboratories implementation of cylinders (MSTAR SLICY) target. Simulation results are provided to demonstrate the effectiveness and robustness of our proposed SAR imaging algorithm.

A striped inductor and its utilization of a voltage-controlled oscillator (VCO) are studied with the aim of suppressing phase noise degradation in K- and Ka-bands. The proposed striped inductor exhibits reduced series resistance in the high frequency region by increasing the cross-sectional peripheral length, as with the Litz wire, and the VCO of the striped inductor simultaneously exhibits a lower phase noise than that of the conventional inductor. Striped and conventional inductors and VCOs are designed and fabricated, and their use of K- and Ka-bands is measured. Results show that the Q factor and corner frequency of the striped inductor are approximately 1.3 and 1.6 times higher, respectively, than that of the conventional inductor. Moreover, the 1-MHz-offset phase noise of the striped inductor's VCO in the K- and Ka-bands was approximately 3.5 dB lower than that of the conventional inductor. In this study, a 65-nm standard CMOS process was used.

An adaptively phase-shift controlled self-injection locked VCO is described. A self-injection locking technique is effective to reduce phase noise. However, a conventional self-injection locked VCO has drawbacks of discontinuous frequency sweep which means narrow bandwidth, and large variation of phase noise. Our proposed adaptively phase-shift controlled self-injection locked VCO overcomes these drawbacks by detecting phase-shift of the self-injection feedback and controlling the phase-shift depending on sweep of the oscillation frequency. This paper describes analysis of relationships between the discontinuity and feedback phase-shift of the self-injection locked VCO. In addition, a VCO-IC which includes a Ka-band VCO and a phase detector is designed and fabricated in 0.18um SiGe BiCMOS technology. Measurement results of the proposed self-injection locked VCO using the fabricated IC show the improvement to the drawbacks. In the proposed self-injection locked VCO, the oscillation frequency sweep is continuous and the phase noise variation is less than 5 dB.