Although baud-rate clock and data recovery (CDR) such as Mueller-Müller (MM) CDR is adopted to ADC-based receivers (RXs), it suffers from false-lock points when the RXs handle PAM4 data pattern because of the absence of edge data. In this paper, a false-lock-aware locking scheme is proposed to address this issue. After the false-lock-aware locking scheme, a clock phase is adjusted to achieve maximum eye height by using a post-1-tap parameter for an FFE in the CDR loop. The proposed techniques are implemented in a 56-Gb/s PAM4 transceiver. A PLL uses an area-efficient “glasses-shaped” inductor. The RX comprises an AFE, a 28-GS/s 7-bit time-interleaved SAR ADC, and a DSP with a 31-tap FFE and a 1-tap DFE. A TX is based on a 7-bit DAC with a 4-tap FFE. The transceiver is fabricated in 16-nm CMOS FinFET technology, and achieves a BER of less than 1e-7 with a 30-dB loss channel. The measurement results show that the MM CDR escapes from false-lock points, and converges to near the optimum point for large eye height.

Many studies of deep neural networks have reported inference accelerators for improved energy efficiency. We propose methods for further improving energy efficiency while maintaining recognition accuracy, which were developed by the co-design of a filter-by-filter quantization scheme with variable bit precision and a hardware architecture that fully supports it. Filter-wise quantization reduces the average bit precision of weights, so execution times and energy consumption for inference are reduced in proportion to the total number of computations multiplied by the average bit precision of weights. The hardware utilization is also improved by a bit-parallel architecture suitable for granularly quantized bit precision of weights. We implement the proposed architecture on an FPGA and demonstrate that the execution cycles are reduced to 1/5.3 for ResNet-50 on ImageNet in comparison with a conventional method, while maintaining recognition accuracy.

This paper presents an ADPLL using a hierarchical TDC composed of a 4fLO DCO followed by a divide-by-4 circuit and three stages of known phase interpolators. We derived simple design requirements for ensuring precision of the phase interpolator. The proposed architecture provides immunity to PVT and local variations, which allows calibration-free operation, as well as sub-inverter delay resolution contributing to good in-band phase noise performance. Also the hierarchical TDC makes it possible to employ a selective activation scheme for power saving. Measured performances demonstrate the above advantages and the in-band phase noise reaches -104 dBc/Hz. It is fabricated in a 65 nm CMOS process and the active area is 0.18 mm2.

In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.