IEICE TRANSACTIONS on Electronics
A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter
Summary :
This paper presents an ADPLL using a hierarchical TDC composed of a 4fLO DCO followed by a divide-by-4 circuit and three stages of known phase interpolators. We derived simple design requirements for ensuring precision of the phase interpolator. The proposed architecture provides immunity to PVT and local variations, which allows calibration-free operation, as well as sub-inverter delay resolution contributing to good in-band phase noise performance. Also the hierarchical TDC makes it possible to employ a selective activation scheme for power saving. Measured performances demonstrate the above advantages and the in-band phase noise reaches -104 dBc/Hz. It is fabricated in a 65 nm CMOS process and the active area is 0.18 mm2.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.6 pp.1008-1016
- Publication Date
- 2012/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.1008
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
Keyword
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Daisuke MIYASHITA, Hiroyuki KOBAYASHI, Jun DEGUCHI, Shouhei KOUSAI, Mototsugu HAMADA, Ryuichi FUJIMOTO, "A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 6, pp. 1008-1016, June 2012, doi: 10.1587/transele.E95.C.1008.
Abstract: This paper presents an ADPLL using a hierarchical TDC composed of a 4fLO DCO followed by a divide-by-4 circuit and three stages of known phase interpolators. We derived simple design requirements for ensuring precision of the phase interpolator. The proposed architecture provides immunity to PVT and local variations, which allows calibration-free operation, as well as sub-inverter delay resolution contributing to good in-band phase noise performance. Also the hierarchical TDC makes it possible to employ a selective activation scheme for power saving. Measured performances demonstrate the above advantages and the in-band phase noise reaches -104 dBc/Hz. It is fabricated in a 65 nm CMOS process and the active area is 0.18 mm2.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.1008/_p
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@ARTICLE{e95-c_6_1008,
author={Daisuke MIYASHITA, Hiroyuki KOBAYASHI, Jun DEGUCHI, Shouhei KOUSAI, Mototsugu HAMADA, Ryuichi FUJIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter},
year={2012},
volume={E95-C},
number={6},
pages={1008-1016},
abstract={This paper presents an ADPLL using a hierarchical TDC composed of a 4fLO DCO followed by a divide-by-4 circuit and three stages of known phase interpolators. We derived simple design requirements for ensuring precision of the phase interpolator. The proposed architecture provides immunity to PVT and local variations, which allows calibration-free operation, as well as sub-inverter delay resolution contributing to good in-band phase noise performance. Also the hierarchical TDC makes it possible to employ a selective activation scheme for power saving. Measured performances demonstrate the above advantages and the in-band phase noise reaches -104 dBc/Hz. It is fabricated in a 65 nm CMOS process and the active area is 0.18 mm2.},
keywords={},
doi={10.1587/transele.E95.C.1008},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter
T2 - IEICE TRANSACTIONS on Electronics
SP - 1008
EP - 1016
AU - Daisuke MIYASHITA
AU - Hiroyuki KOBAYASHI
AU - Jun DEGUCHI
AU - Shouhei KOUSAI
AU - Mototsugu HAMADA
AU - Ryuichi FUJIMOTO
PY - 2012
DO - 10.1587/transele.E95.C.1008
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2012
AB - This paper presents an ADPLL using a hierarchical TDC composed of a 4fLO DCO followed by a divide-by-4 circuit and three stages of known phase interpolators. We derived simple design requirements for ensuring precision of the phase interpolator. The proposed architecture provides immunity to PVT and local variations, which allows calibration-free operation, as well as sub-inverter delay resolution contributing to good in-band phase noise performance. Also the hierarchical TDC makes it possible to employ a selective activation scheme for power saving. Measured performances demonstrate the above advantages and the in-band phase noise reaches -104 dBc/Hz. It is fabricated in a 65 nm CMOS process and the active area is 0.18 mm2.
ER -
English
