A novel automatic quality factor (Q) tuning scheme for an low-power and wideband active-RC filter is presented. Although Q-tuning is effective to reduce the power consumption of wideband active-RC filters, there are several problems since the Q-tuning normally relies on a magnitude locked loop (MLL). MLL is not accurate due to the amplitude detection circuits, and occupied area and power consumption tends to be large due to its complexity. In addition, flexibility to the reference signal may be the problem, since the reference signal which has a fixed accurate frequency is required. In order to solve these problems, we propose a Q-tuning scheme, which does not require a MLL. Therefore, proposed Q-tuning scheme has good accuracy, small die area, low power consumption and flexibility to the reference signal. In our proposed scheme, Q is tuned by adjusting the phase of an integrator to 90 degrees. The phase of an integrator is adjusted by detecting and controlling the oscillation frequency of a two-stage ring-integrator to the cutoff frequency of a filter, since the phase shift of an integrator is exactly 90 degrees at the oscillation frequency. The frequency is easily detected and controlled by counters and variable resistors, respectively. The Q-tuning circuit with a 5th-order Chebyshev LPF is implemented in a 0.13 µm CMOS technology. The tuning circuit occupies 0.12 mm2 and consumes 2.6 mW from 1.2 V supply.

A frequency drift of open-loop PLL is an issue for the direct-modulation applications such as Bluetooth transceiver. The drift mainly comes from a temperature variation of VCO during the transmission operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through the whole-chip thermal analysis. Moreover, a novel temperature-compensated VCO, employing a new biasing scheme, is proposed. The combination of these two techniques enables the power reduction of the transmitter by 33% without sacrificing the performance.

A wideband, low noise, and highly linear transmitter for multi-mode radio is presented. Envelope injection scheme with a CMOS amplifier is developed to obtain sufficient linearity for complex modulation schemes such as OFDM, and to achieve low noise for concurrent operation of more than one standard. Active matching technique with doubly terminated LPF topology is also presented to realize wide bandwidth, low power consumption, and to eliminate off-chip components without increasing die area. A multi-mode transmitter is implemented in a 0.13 µm CMOS technology with an active area of 1.13 mm2. Third-order intermodulation product is improved by 17 dB at -3 dBm output by the envelope injection scheme. The transmitter achieves EVM of less than -29.5 dB at -3 dBm output from 0.2 to 7.2 GHz while consuming only 69 mW. The transmitter is also tested with multiple standards of UMTS, 802.11b, WiMax, 802.11a, and 802.11n, and satisfies EVM, ACLR, and spectrum specifications.

This paper presents an ADPLL using a hierarchical TDC composed of a 4fLO DCO followed by a divide-by-4 circuit and three stages of known phase interpolators. We derived simple design requirements for ensuring precision of the phase interpolator. The proposed architecture provides immunity to PVT and local variations, which allows calibration-free operation, as well as sub-inverter delay resolution contributing to good in-band phase noise performance. Also the hierarchical TDC makes it possible to employ a selective activation scheme for power saving. Measured performances demonstrate the above advantages and the in-band phase noise reaches -104 dBc/Hz. It is fabricated in a 65 nm CMOS process and the active area is 0.18 mm2.

This paper describes a full-CMOS single-chip Bluetooth LSI fabricated using a 0.18 µm CMOS, triple-well, quad-metal technology. The chip integrates radio and baseband, which is compliant with Bluetooth Core Specification version 1.1. A direct modulation transmitter and a low-IF receiver architecture are employed for the low-power and low-cost implementation. To reduce the power consumption of the digital blocks, it uses a clock gating technique during the active modes and a power manager during the low power modes. The maximum power consumption is 75 mW for the transmission, 120 mW for the reception and 30 µW for the low power mode operation. These values are low enough for mobile applications. Sensitivity of -80 dBm has been achieved and the transmitter can deliver up to 4 dBm.