A frequency drift of open-loop PLL is an issue for the direct-modulation applications such as Bluetooth transceiver. The drift mainly comes from a temperature variation of VCO during the transmission operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through the whole-chip thermal analysis. Moreover, a novel temperature-compensated VCO, employing a new biasing scheme, is proposed. The combination of these two techniques enables the power reduction of the transmitter by 33% without sacrificing the performance.

We have proposed the high-density triangular parallel wire channel MOSFET on an SOI substrate and demonstrated the suppressed short channel effects by simulation and experiment. In this device structure, the fabrication process is fully compatible with the planar MOSFET process and is much less complicated than other non-planer device structures including gate-all-around (GAA) and double-gate SOI MOSFETs. In addition, our fabrication process makes it possible to double the wire density resulting in the higher current drive. The three-dimensional simulation results show that the proposed triangular wire channel MOSFET has better short channel characteristics than single-gate and double-gate SOI MOSFETs. The fabricated triangular parallel wire channel MOSFETs show better subthreshold characteristics and less drain induced barrier lowering (DIBL) than the single-gate SOI MOSFETs.

Various techniques of single-electron circuit simulation are presented. The subjects include visualization of state probabilities, accurate yet reasonably fast steady-state analysis and SPICE-based high-speed simulation for circuits composed of Single-Electron Transistors (SETs). The visualized state probabilities allow one to grasp the dynamics of a single-electron circuit intuitively. The new algorithm for steady-state analysis uses the master equation and Monte Carlo method in combination. We suppose this is the best way to perform steady-state analysis. The SPICE-based simulator significantly outperforms the conventional reference simulator in speed. It is, to the best of our knowledge, the only simulator that can simulate SET circuits for real applications. It also facilitates the study of the integration of SETs and MOSFETs.

A 2.4 GHz 0.13 µm CMOS transceiver LSI, supporting Bluetooth V2.1+enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40 and +90. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90 dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13 µm CMOS and operation at a low supply voltage of 1.5 V result in small area and low power consumption.