A striped inductor and its utilization of a voltage-controlled oscillator (VCO) are studied with the aim of suppressing phase noise degradation in K- and Ka-bands. The proposed striped inductor exhibits reduced series resistance in the high frequency region by increasing the cross-sectional peripheral length, as with the Litz wire, and the VCO of the striped inductor simultaneously exhibits a lower phase noise than that of the conventional inductor. Striped and conventional inductors and VCOs are designed and fabricated, and their use of K- and Ka-bands is measured. Results show that the Q factor and corner frequency of the striped inductor are approximately 1.3 and 1.6 times higher, respectively, than that of the conventional inductor. Moreover, the 1-MHz-offset phase noise of the striped inductor's VCO in the K- and Ka-bands was approximately 3.5 dB lower than that of the conventional inductor. In this study, a 65-nm standard CMOS process was used.

A 2.4 GHz 0.13 µm CMOS transceiver LSI, supporting Bluetooth V2.1+enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40 and +90. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90 dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13 µm CMOS and operation at a low supply voltage of 1.5 V result in small area and low power consumption.

This report focuses on an optimization scheme of advanced MOSFETs for designing CMOS circuits with high power efficiency. For this purpose the physics-based compact model HiSIM2 is applied so that the relationship between device and circuit characteristics can be investigated properly. It is demonstrated that the short-channel effect, which is usually measured by the threshold-voltage shift relative to long-channel MOSFETs, provides a consistent measure for device-performance degradation with reduced channel length. However, performance degradations of CMOS circuits such as the power loss cannot be predicted by the threshold-voltage shift alone. Here, the subthreshold swing is identified as an additional important measure for power-efficient CMOS circuit design. The increase of the subthreshold swing is verified to become obvious when the threshold-voltage shift is larger than 0.15V.

This paper presents the strategy of MOS varactor's high-Q optimization, a novel scalable model for the quasi-millimeter-wave MOS varactors, and confirmation results by discrete MOS varactors and VCO measurements. To realize a high-Q MOS varactor in the quasi-millimeter-wave region, low MOS varactor capacitance and low series resistance of unit cell are essential. Downsizing is a key to realize both low capacitance and low resistance. However, it is induced by Cmax/Cmin reduction, simultaneously. Therefore, scalable MOS varactor model is necessary to use optimum MOS varactor to cover various application requirements using same process. Decreasing the MOS varactor's size of W/L =2µm/2µm to 0.5µm/0.26µm, the Q factor increased sevenfold at f =20GHz but Cmax/Cmin is reduced by 60%, by using conventional PSP model, an error of approximately 20% is shown. Proposed model has been improved its accuracy from 18.9% to 0.2% for N+ MOS varactor and from 22.1% to 0.8% for P+ MOS varactor, for minimum size of MOS varactor even if model covers wide dimension range. Also, it has been confirmed this model is covered in two types of layouts. Oscillation frequency and phase noise also have been confirmed by three types of 22GHz VCOs. The accuracy of oscillation frequency is less than 2.5% and that of phase noise at 1MHz offset from carrier is less than 5dB.