In this paper, we report the detailed investigation of novel printed disc monopole antennas for ultra-wideband (UWB) applications focusing on miniaturization of the disc radiator. First, the basic property was examined for the case of a circular disc with diameter of 50 mm, and it was found that the VSWR is less than 2 in the UWB band of 3.1-10.6 GHz when the feed gap length is between about -0.1 and 0.2 mm. Next, in order to reduce the size of the disc radiator, various dimensions of elliptical discs were investigated. It is shown that if the dimensions of the elliptical disc are chosen appropriately, a smaller disc size antenna can be achieved. To decrease the antenna size further, a triangular notch and an exponentially curved notch on the ground plane of the antenna were examined. It is observed that the use of the notched ground is very effective and that the diameter of the circular radiator can be reduced to 17 mm. The proposed antenna has an omnidirectional pattern in the x-y plane. The influence of the notch on the radiation pattern is very small. Details of the simulation results using the FDTD method and experimental results for the proposed antenna are presented and analyzed. These features are very attractive for UWB applications.

In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.

This paper devises a sophisticated approach to the performance estimation of an embedded hardware-software codesign system at the architecture level, which intends to optimize the hardware-software configuration in terms of processing time, power dissipation, and hardware cost. A distinctive feature of this approach consists in constructing a performance estimation model proper to each component of an embedded system, such as CPU core, RAM/ROM, cache memory, and application-specific hardware, by taking account of not only the functional performance but also the data transfer. The proposed estimation schemes are incorporated into an existing instruction set simulator, so that the actual performance can be estimated accurately at the architecture level. The experimental results demonstrate that the performance estimation approach enables the precise design decision at the architecture level, which greatly contributes toward enhancing the design ability dedicatedly for mobile appliances.

This paper describes a full-CMOS single-chip Bluetooth LSI fabricated using a 0.18 µm CMOS, triple-well, quad-metal technology. The chip integrates radio and baseband, which is compliant with Bluetooth Core Specification version 1.1. A direct modulation transmitter and a low-IF receiver architecture are employed for the low-power and low-cost implementation. To reduce the power consumption of the digital blocks, it uses a clock gating technique during the active modes and a power manager during the low power modes. The maximum power consumption is 75 mW for the transmission, 120 mW for the reception and 30 µW for the low power mode operation. These values are low enough for mobile applications. Sensitivity of -80 dBm has been achieved and the transmitter can deliver up to 4 dBm.

This letter proposes an efficient lossless compression method for high dynamic range (HDR) images in OpenEXR format. The proposed method transforms an HDR image to an indexed image and packs the histogram of the indexed image. Finally the packed image is losslessly compressed by using any existing lossless compression algorithm such as JPEG 2000. Experimental results show that the proposed method reduces the bit rate of compressed OpenEXR images compared with equipped lossless compression methods of OpenEXR format.

Although baud-rate clock and data recovery (CDR) such as Mueller-Müller (MM) CDR is adopted to ADC-based receivers (RXs), it suffers from false-lock points when the RXs handle PAM4 data pattern because of the absence of edge data. In this paper, a false-lock-aware locking scheme is proposed to address this issue. After the false-lock-aware locking scheme, a clock phase is adjusted to achieve maximum eye height by using a post-1-tap parameter for an FFE in the CDR loop. The proposed techniques are implemented in a 56-Gb/s PAM4 transceiver. A PLL uses an area-efficient “glasses-shaped” inductor. The RX comprises an AFE, a 28-GS/s 7-bit time-interleaved SAR ADC, and a DSP with a 31-tap FFE and a 1-tap DFE. A TX is based on a 7-bit DAC with a 4-tap FFE. The transceiver is fabricated in 16-nm CMOS FinFET technology, and achieves a BER of less than 1e-7 with a 30-dB loss channel. The measurement results show that the MM CDR escapes from false-lock points, and converges to near the optimum point for large eye height.

We proposed a method for embedding binary data into JPEG bitstreams and extracting embedded data from JPEG bitstreams using the standard JPEG decoder. In the proposed method, we can decode the image from JPEG bitstreams into which the binary data is embedded first using the traditional standard JPEG decoder, and then we can extract the embedded binary data perfectly by the post-processing from the decoded JPEG image. For the post-processing, we use only the decoded image data to extract the embedded binary data. Namely, we do not need any kind of particular parameters, which are used for JPEG decoding, such as quantization table value. Thus, we can use the traditional standard JPEG decoder for the pre-processing of extracting binary data. Furthermore, we address the effect of the calculation bit accuracy of discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) for extracting embedded binary data perfectly as post-processing. Simulations using extracting embedded binary data as post-processing are presented to quantify some performance factors concerned. And we confirmed that the proposed method could be of practical use.

A method to derive design rules for SSO (Simultaneous Switching Outputs) considering jitter constraint on LSI outputs is proposed. Since conventional design rules do not consider delay change caused by SSO, timing errors have sometimes occurred in output signals especially for a high-speed memory interface which allows very small jitter. A design rule derived by the proposed method includes delay change characteristics of output buffers to consider the jitter constraint. The rule also gives mapping from the jitter constraint to constraint on design parameters such as effective power/ground inductance, number of SSO and drivability of buffers.

A frequency drift of open-loop PLL is an issue for the direct-modulation applications such as Bluetooth transceiver. The drift mainly comes from a temperature variation of VCO during the transmission operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through the whole-chip thermal analysis. Moreover, a novel temperature-compensated VCO, employing a new biasing scheme, is proposed. The combination of these two techniques enables the power reduction of the transmitter by 33% without sacrificing the performance.

An efficient two-layer coding method using the histogram packing technique with the backward compatibility to the legacy JPEG is proposed in this paper. The JPEG XT, which is the international standard to compress HDR images, adopts two-layer coding scheme for backward compatibility to the legacy JPEG. However, this two-layer coding structure does not give better lossless performance than the other existing methods for HDR image compression with single-layer structure. Moreover, the lossless compression of the JPEG XT has a problem on determination of the coding parameters; The lossless performance is affected by the input images and/or the parameter values. That is, finding appropriate combination of the values is necessary to achieve good lossless performance. It is firstly pointed out that the histogram packing technique considering the histogram sparseness of HDR images is able to improve the performance of lossless compression. Then, a novel two-layer coding with the histogram packing technique and an additional lossless encoder is proposed. The experimental results demonstrate that not only the proposed method has a better lossless compression performance than that of the JPEG XT, but also there is no need to determine image-dependent parameter values for good compression performance without losing the backward compatibility to the well known legacy JPEG standard.

In this letter, we discuss the impact of intrinsic error in parasitic capacitance extraction programs which are commonly used in today's SoC design flows. Most of the extraction programs use pattern-matching methods which introduces an improvable error factor due to the pattern interpolation, and an intrinsically inescapable error factor from the difference of boundary conditions in the electro-magnetic field solver. Here, we study impact of the intrinsic error on timing and crosstalk noise estimation. We experimentally show that the resulting delay and noise estimation errors show a scatter which is normally distributed. Values of the standard deviations will help designers consider the intrinsic error compared with other variation factors.

With the recent advance of process technology shrinking, process parameter variation has become one of the major issues in SoC designs, especially for timing convergence. Recently, Statistical Static Timing Analysis (SSTA) has been proposed as a promising solution to consider the process parameter variation but it has not been widely used yet. For estimating the delay yield, designers have to know and understand the accuracy of SSTA. However, the accuracy has not been thoroughly studied from a practical point of view. This paper proposes two metrics to measure the pessimism/optimism of SSTA; the first corresponds to yield estimation error, and the second examines delay estimation error. We apply the metrics for a problem which has been widely discussed in SSTA community, that is, normal-distribution approximation of max operation. We also apply the proposed metrics for benchmark circuits and discuss about a potential problem originating from normal-distribution approximation. Our metrics indicate that the appropriateness of the approximation depends on not only given input distributions but also the target yield of the product, which is an important message for SSTA users.

A 2.4 GHz 0.13 µm CMOS transceiver LSI, supporting Bluetooth V2.1+enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40 and +90. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90 dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13 µm CMOS and operation at a low supply voltage of 1.5 V result in small area and low power consumption.

This paper discusses a method of designing linear phase two-channel filter banks for integer wavelet transform. We show that the designed filter banks are easily structed as the lifting form by leading relationship between designed filters and lifting structure. The designed integer wavelets are applied to image compression to verify the efficiency of our method.

In many applications of digital video database systems such as digital library, video data is often compressed with MPEG video algorithms. It will be an important technique to insert the additional information data like indexes and contents effectively into video database which is compressed with MPEG, because we can always deal with the additional information with video data itself easily. We propose a method for inserting optional binary data such as index information of digital library into MPEG-1 and -2 bitstreams. The binary data inserted MPEG video bitstreams using our proposed scheme are also according to the specification of the MPEG video frame structure. The proposed method allows us to extract the inserted binary data perfectly though MPEG-1 and -2 video are lossy algorithms. And the quality of decoded images after extracting added information is almost the same as that of ordinary MPEG bitstreams. Furthermore, traditional standard MPEG-1 and -2 video decoder which can not extract inserted binary data can also decode images from the binary data inserted MPEG video bitstreams without obvious image degradation. There are some different points between the proposed insertion technique of the binary data and the watermarking technique. The technique of watermarking prepares to deal with alter watermarking by others. And the technique of watermarking is required for the identification of the signature and the perfect extraction of the inserted image signature is not required in the lossy MPEG video environment. On the other hand, we have to extract all of the inserted binary information data correctly with the insertion technique of the binary information. Simulations using MPEG video sequences with inserted binary data are presented to quantify some performance factors concerned. We have not heard about inserting data method which purpose is such as index and content information insertion.

We propose an efficient two-layer near-lossless coding method using an extended histogram packing technique with backward compatibility to the legacy JPEG standard. The JPEG XT, which is the international standard to compress HDR images, adopts a two-layer coding method for backward compatibility to the legacy JPEG standard. However, there are two problems with this two-layer coding method. One is that it does not exhibit better near-lossless performance than other methods for HDR image compression with single-layer structure. The other problem is that the determining the appropriate values of the coding parameters may be required for each input image to achieve good compression performance of near-lossless compression with the two-layer coding method of the JPEG XT. To solve these problems, we focus on a histogram-packing technique that takes into account the histogram sparseness of HDR images. We used zero-skip quantization, which is an extension of the histogram-packing technique proposed for lossless coding, for implementing the proposed near-lossless coding method. The experimental results indicate that the proposed method exhibits not only a better near-lossless compression performance than that of the two-layer coding method of the JPEG XT, but also there are no issue regarding the combination of parameter values without losing backward compatibility to the JPEG standard.

This paper presents an ADPLL using a hierarchical TDC composed of a 4fLO DCO followed by a divide-by-4 circuit and three stages of known phase interpolators. We derived simple design requirements for ensuring precision of the phase interpolator. The proposed architecture provides immunity to PVT and local variations, which allows calibration-free operation, as well as sub-inverter delay resolution contributing to good in-band phase noise performance. Also the hierarchical TDC makes it possible to employ a selective activation scheme for power saving. Measured performances demonstrate the above advantages and the in-band phase noise reaches -104 dBc/Hz. It is fabricated in a 65 nm CMOS process and the active area is 0.18 mm2.