IEICE TRANSACTIONS on Fundamentals
A Method to Derive SSO Design Rule Considering Jitter Constraint
Summary :
A method to derive design rules for SSO (Simultaneous Switching Outputs) considering jitter constraint on LSI outputs is proposed. Since conventional design rules do not consider delay change caused by SSO, timing errors have sometimes occurred in output signals especially for a high-speed memory interface which allows very small jitter. A design rule derived by the proposed method includes delay change characteristics of output buffers to consider the jitter constraint. The rule also gives mapping from the jitter constraint to constraint on design parameters such as effective power/ground inductance, number of SSO and drivability of buffers.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.4 pp.865-872
- Publication Date
- 2006/04/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.4.865
- Type of Manuscript
- Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Category
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Koutaro HACHIYA, Hiroyuki KOBAYASHI, Takaaki OKUMURA, Takashi SATO, Hiroki OKA, "A Method to Derive SSO Design Rule Considering Jitter Constraint" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 4, pp. 865-872, April 2006, doi: 10.1093/ietfec/e89-a.4.865.
Abstract: A method to derive design rules for SSO (Simultaneous Switching Outputs) considering jitter constraint on LSI outputs is proposed. Since conventional design rules do not consider delay change caused by SSO, timing errors have sometimes occurred in output signals especially for a high-speed memory interface which allows very small jitter. A design rule derived by the proposed method includes delay change characteristics of output buffers to consider the jitter constraint. The rule also gives mapping from the jitter constraint to constraint on design parameters such as effective power/ground inductance, number of SSO and drivability of buffers.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.4.865/_p
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@ARTICLE{e89-a_4_865,
author={Koutaro HACHIYA, Hiroyuki KOBAYASHI, Takaaki OKUMURA, Takashi SATO, Hiroki OKA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Method to Derive SSO Design Rule Considering Jitter Constraint},
year={2006},
volume={E89-A},
number={4},
pages={865-872},
abstract={A method to derive design rules for SSO (Simultaneous Switching Outputs) considering jitter constraint on LSI outputs is proposed. Since conventional design rules do not consider delay change caused by SSO, timing errors have sometimes occurred in output signals especially for a high-speed memory interface which allows very small jitter. A design rule derived by the proposed method includes delay change characteristics of output buffers to consider the jitter constraint. The rule also gives mapping from the jitter constraint to constraint on design parameters such as effective power/ground inductance, number of SSO and drivability of buffers.},
keywords={},
doi={10.1093/ietfec/e89-a.4.865},
ISSN={1745-1337},
month={April},}
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TY - JOUR
TI - A Method to Derive SSO Design Rule Considering Jitter Constraint
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 865
EP - 872
AU - Koutaro HACHIYA
AU - Hiroyuki KOBAYASHI
AU - Takaaki OKUMURA
AU - Takashi SATO
AU - Hiroki OKA
PY - 2006
DO - 10.1093/ietfec/e89-a.4.865
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2006
AB - A method to derive design rules for SSO (Simultaneous Switching Outputs) considering jitter constraint on LSI outputs is proposed. Since conventional design rules do not consider delay change caused by SSO, timing errors have sometimes occurred in output signals especially for a high-speed memory interface which allows very small jitter. A design rule derived by the proposed method includes delay change characteristics of output buffers to consider the jitter constraint. The rule also gives mapping from the jitter constraint to constraint on design parameters such as effective power/ground inductance, number of SSO and drivability of buffers.
ER -
English
