Power supply noise generated by integrated circuits is one of the major sources of electromagnetic radiation from printed circuit boards (PCB). The reduction of power supply noise can be realized by means of devices that bypass the current among power supply planes, such as bypass capacitors and ground vias. In the present work, the effect of current bypass devices on the far field radiation from multilayer PCBs is represented in terms of the ratio between the far field after and before their introduction, and it is estimated by means of the power transported by the ‘radiation effective forward wave’ in infinite power supply planes. This approach is computationally very efficient and yelds improved EMC designs for power supply planes in realistic PCBs, for example by selecting the position of stitching ground vias. The results are confirmed by a comparison with commercial tools. Forward wave analysis can be used also to study the vertical distribution of the power supply noise in multilayer PCBs. This allows to understand some important noise propagation mechanisms that are related to power and signal integrity as well, and to take low-cost countermeasures at early stage of PCB design.

In this paper, a novel method of partially placing electromagnetic band-gap (EBG) unit cells on both the power and ground planes in multi-layer PCBs and packages is proposed; it can not only sufficiently eliminate simultaneous switching noise (SSN), but also prevent severe degradation of signal quality in high-speed systems with imperfect reference planes resulting from the perforated structures of uni-planar EBG unit cells. On the assumption that the noise sources and noise-sensitive devices exist only in specific areas, the proposed method partially arranges the EBG unit cells on both the power and ground planes, but only around the critical areas. The SSN suppression performance of the proposed structure is verified by a simulation and measurements.

To build a stable power distribution network for high-speed digital systems, simultaneous switching noise (SSN) should be sufficiently suppressed in multi-layer PCBs and packages. In this paper, a novel hybrid uni-planar compact electromagnetic bandgap (UC-EBG) with two triangular-type unit cells designed on power/ground planes is proposed for the ultra-broadband suppression of SSN. The SSN suppression performance of the proposed structure is validated both numerically and experimentally. A -35 dB suppression bandwidth for SSN is achieved, starting at 800 MHz and extending to 15 GHz and beyond, thereby covering almost the entire noise band.

Power and ground planes on multilayer PCBs can effectively radiate electromagnetic fields excited by the IC simultaneous switching noise. The high frequency electromagnetic radiation is often calculated from the electric field along the edge of the PCB, which can be estimated with a cavity model using magnetic walls. The excitation of the cavity modes is related to the via current passing through the power bus planes at the interconnection between IC package and PCB. Usually the attention is focused on the differential-mode current of the package pins, but in the present paper it is shown that the common-mode current flowing out from package pins plays a very important role in the excitation of cavity modes, and its neglect implies a fatal underestimation of the electromagnetic radiation from the power bus planes in some circumstances. A second important contribute to the radiation is given by the common mode current on the pins, together with the current flowing on the PCB ground plane. With the proposed equivalent circuit, the effectiveness of decoupling inductors depending on their location and on the value of the parasitic capacitance is studied.

A general-purpose multi-Gbps LVDS driver is presented with a new distortion-free level conversion scheme. For high-speed transmission, a dynamic pre-emphasis scheme is also proposed with overdriving current effectively distributed in time. The proposed LVDS driver achieves supply-insensitive duty preservation with a reduction of switching noise by 50-percent.

A method to derive design rules for SSO (Simultaneous Switching Outputs) considering jitter constraint on LSI outputs is proposed. Since conventional design rules do not consider delay change caused by SSO, timing errors have sometimes occurred in output signals especially for a high-speed memory interface which allows very small jitter. A design rule derived by the proposed method includes delay change characteristics of output buffers to consider the jitter constraint. The rule also gives mapping from the jitter constraint to constraint on design parameters such as effective power/ground inductance, number of SSO and drivability of buffers.

This paper reports experimental results on far-field radiated emission for different on-chip chip power supply networks. Two types of test chips were developed as noise generators. One was with on-chip decoupling capacitance, and the other was without intentional on-chip decoupling capacitance. They were assembled in a CSP (Chip scale package). The effects of on-chip decoupling capacitance on far-field radiated emission were investigated for the operation of core logic circuits and output buffer circuits. Reduced radiated emission was observed for every harmonics for the operation of core logic circuits by the on-chip decoupling capacitance. While, reduced radiated emission was observed for the even-order harmonics for the operation of output buffer circuits due to the existence of on-chip decoupling capacitance.

This letter proposes an output driver which reduces simultaneous switching noise without degradation of rise/fall time. At the start of transition period, the driver optimally uses both VDD and VSS current by switching of on-chip bypass capacitors. The proposed driver achieves 27-percent reduction in peak current with faster transition time.

We have thoroughly investigated the effect of on-chip decoupling capacitors on the simultaneous switching noise (SSN) and the radiated emission. Furthermore, we have successfully demonstrated an efficient design method for on-chip decoupling capacitors on an 8-bit microcontroller without increasing the die size, which results in more than 10 dB of suppressed radiated emission.

We derive an efficient and simple analytical expression for estimating maximum simultaneous switching noise (SSN) on ground distribution networks in CMOS systems. In order to estimate maximum SSN voltages, we use α-power law MOS model and Taylor's series approximation. The accuracy of the proposed expression is verified by comparing the results with those of previous researches and HSPICE simulations under the contemporary process parameters and environmental conditions. The proposed method predicts the maximum SSN values more accurately when compared to existing approaches even in most practical cases such that there exist some output drivers not in transition.

This paper presents an efficient method for estimating maximum simultaneous switching noise (SSN) of ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression we use α-power law MOS model and an iterative method to reduce error that may occur due to the assumptions used in the derivation process. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the present process parameters and environmental conditions.