This paper reports experimental results on far-field radiated emission for different on-chip chip power supply networks. Two types of test chips were developed as noise generators. One was with on-chip decoupling capacitance, and the other was without intentional on-chip decoupling capacitance. They were assembled in a CSP (Chip scale package). The effects of on-chip decoupling capacitance on far-field radiated emission were investigated for the operation of core logic circuits and output buffer circuits. Reduced radiated emission was observed for every harmonics for the operation of core logic circuits by the on-chip decoupling capacitance. While, reduced radiated emission was observed for the even-order harmonics for the operation of output buffer circuits due to the existence of on-chip decoupling capacitance.

Thin-film multichip modules fabricated by chip-on-wafer (COW) technology have been developed for high performance systems. Copper/polyimide thin-film wiring layers are fabricated on a silicon substrate. LSI chips with copper-cored solder bumps (CCSBs) are flip-chip bonded to the silicon substrate. The substrate is housed in a co-fired aluminum nitride (AlN) ceramic package to enhance thermal reliability. The electrical properties, such as the characteristic impedance and crosstalk noise, of the copper/polyimide wiring substrate were examined. Experimental results have shown that the substrate can propagate high-speed signals exceeding 100 MHz. Next, this combination of a large silicon substrate and an AlN package was investigated thermally and mechanically. The results of warping tests and thermal cycling tests show that AlN is an excellent packaging material for silicon-based multichip modules. A digital signal processing module has been developed as an example of a high-performance multichip module.

Multichip modules (MCM's) have been actively developed in recent years. They are expected to provide high-performance systems by packing bare chips at a high density. In particular, a thin-film interconnect substrate that can accommodate higher wiring capacity in a few layers is a new option for coping with high pin count and fine pad pitch VLSI's. MCM's require various kinds of technologies including the fabrication processes of interconnect substrates, chip connection methods, electrical design, thermal management, known good die (KGD), and so on. The state of the art of MCM technologies is reviewed and future directions are discussed.