Precision microwave measurement systems require highly stable oscillators with both excellent long-term and short-term stability. Compared to components used in laboratory instruments, dielectric resonator oscillators (DRO) offer low phase noise with greatly reduced mechanical complexity. To further enhance performance, phase-locked loop (PLL) stabilization can be used to eliminate drift and provide precise frequency control. In this work, the design of a low-cost DRO concept is presented and its performance is evaluated through simulations and measurements. An open-loop phase noise of -107.2 dBc/Hz at 10 kHz offset frequency and 12.8 GHz output frequency is demonstrated. Drift and phase noise are reduced by a PLL, so that a very low jitter of under 29.6 fs is achieved over the entire operating bandwidth.

Autonomous driving technology is expected to be applied to various applications with unmanned vehicles (UVs), such as small delivery vehicles for office supplies and smart wheelchairs. UV remote control by a cloud server (CS) would achieve cost-effective applications with a large number of UVs. In general, dead time in real-time feedback control reduces the control accuracy. On remote path tracking control by the CS, UV control accuracy deteriorates due to transmission delay and jitter through the Internet. Digital twin computing (DTC) and jitter buffer are effective to solve this problem. In our previous study, we clarified effectiveness of them in UV remote control by CS. The jitter buffer absorbs the transmission delay jitter of control signals. This is effective to achieve accurate UV remote control. Adaptive buffering time optimization according to real-time transmission characteristics is necessary to achieve more accurate UV control in CS-based remote control system with DTC and jitter buffer. In this study, we proposed a method for the adaptive optimization according to real-time transmission delay characteristics. To quantitatively evaluate the effectiveness of the method, we created a UV remote control simulator of the control system. The results of simulations quantitatively clarify that the adaptive optimization by the proposed method improves the UV control accuracy.

In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.

With increasing technology scaling and the use of lower voltages, more research interest is being shown in variability-tolerant analog front end design. In this paper, we describe an adaptive amplitude control transmitter that is operated using differential signaling to reduce the temperature variability effect. It enables low power, low voltage operation by synergy between adaptive amplitude control and Vth temperature variation control. It is suitable for high-speed interface applications, particularly cable interfaces. By installing an aggressor circuit to estimate transmitter jitter and changing its frequency and activation rate, we were able to analyze the effects of the interface block on the input buffer and thence on the entire system. We also report a detailed estimation of the receiver clock-data recovery (CDR) operation for transmitter jitter estimation. These investigations provide suggestions for widening the eye opening of the transmitter.

The optical-transition edge sensors are single-photon detectors that can determine photon energies at visible to telecommunication wavelengths. They offer a high detection efficiency and negligible dark count, which are very attractive qualities for applications in quantum optics or bioimaging. This study reviews the operating principles of such detectors and the current status of their development.

Timing vernier (i.e., digital-to-time converter) is a key component of the pin-electronics circuit board installed in automated digital-VLSI test equipment, and it is used to create fine delays of less than one-cycle time of a clock signal. This paper presents a new on-the-fly (timing-) jitter suppression technique which makes it possible to use low-power plain-CMOS-logic-based timing verniers. Using a power-compensation line installed at the poststage of the digitally variable delay line, we make every pulse (used as a timing signal) consume a fixed amount of electric energy independent of the required delay amount. Since the power load of intrapowerlines is kept constantly, the jitter increase in the situation of changing the required delay amount on the fly is suppressed. On the basis of the concept, a 10-ns span, 125-MHz timing-vernier macro was designed and fabricated with a CMOS process for logic VLSIs. Every macro installed in a real-time timing-signal generator VLSI achieved the required timing resolution of 31.25ps with a linearity error within 15ps. The on-the-fly jitter was successfully suppressed to a random jitter level (<26ps p-p).

This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm2). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (VDD =0.52 V), the ADPLL only dissipates 269.9 μW at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of -57.3 dBc with the period jitter of 0.217% UI.

This paper presents a cell-based all-digital phase-locked loop (ADPLL) with hierarchical gated digitally controlled oscillator (G-DCO) for low voltage operation, wide frequency range as well as low-power consumption. In addition, a new time-domain hierarchical frequency estimation algorithm (HFEA) for frequency acquisition is proposed to estimate the output frequency in 1.5MF (MF = 3 in this paper) cycles and this fast lock-in time is suitable to the dynamic voltage frequency scaling (DVFS) systems. A hierarchical G-DCO is proposed to work at low supply voltage to reduce the power consumption and at the same time to achieve wide frequency range and precise frequency resolution. The core area of the proposed ADPLL is 0.02635 mm2. In near-threshold region (VDD = 0.36 V), the proposed ADPLL only dissipates 68.2 µW and has a rms period jitter of 1.25% UI at 60 MHz output clock frequency. Under 0.5 V VDD operation, the proposed ADPLL dissipates 404.2 µW at 400 MHz. The fast lock-in time of 4.489 µs and the low jitter performance below 0.5% UI at 400 MHz output clock frequency in the proposed ADPLL are suitable in event-driven or DVFS applications.

We present a low-jitter design for a 10-bit second-order frequency shift oscillator time-to-digital converter (FSOTDC). As described herein, we analyze the relation between performance and FSOTDC parameters and provide insight to support the design of the FSOTDC. Results show that an oscillator jitter limits the FSOTDC resolution, particularly during the first stage. To estimate and design an FSOTDC, the frequency shift oscillator requires an inverter of a certain size. In a standard 65-nm CMOS process, an SNDR of 64dB is achievable at an input signal frequency of 10kHz and a sampling clock of 2MHz. Measurements of the test chip confirmed that the measurements match the analyses.

This paper studies the performance of code-aided (CA) soft-information based carrier phase recovery, which iteratively exploits the extrinsic information from channel decoder to improve the accuracy of phase synchronization. To tackle the problem of strong coupling between phase recovery and decoding, a semi-analytical model is proposed to express the distribution of extrinsic information as a function of phase offset. Piecewise approximation of the hyperbolic tangent function is employed to linearize the expression of soft symbol decision. Building on this model, open-loop characteristic and closed-loop performance of CA iterative soft decision-directed (ISDD) carrier phase synchronizer are derived in closed-form. Monte Carlo simulation results corroborate that the proposed expressions are able to characterize the performance of CA ISDD carrier phase recovery for systems with different channel codes.

To achieve high recording density in a bit-patterned media recording system, the spacing between data bit islands in both the along-track and the across-track directions must be decreased, thus leading to the increase of two-dimensional (2D) interference. One way to reduce the 2D interference is to apply a 2D coding scheme on a data sequence before recording; however, this method usually requires many redundant bits, thus lowering a code rate. Therefore, we propose a novel 2D coding scheme referred to as a recorded-bit patterning (RBP) scheme to mitigate the 2D interference, which requires no redundant bits at the expense of using more buffer memory. Specifically, an input data sequence is first split into three tracks in which will then be rotated to find the best 3-track data pattern based on a look-up table before recording, such that the shifted data tracks yield the least effect of 2D interference in the readback signal. Numerical results indicate that the proposed RBP scheme provides a significant performance improvement if compared to a conventional system (without 2D coding), especially when the recording density is high and/or the position jitter noise is large.

We propose a jitter amplifier architecture for an oscillator-based true random number generator (TRNG). Two types of latency-controllable (LC) buffer, which are the key components of the proposed jitter amplifier, are presented. We derive an equation to estimate the gain of the jitter amplifier, and analyze sufficient conditions for the proposed circuit to work properly. The proposed jitter amplifier was fabricated with a 65 nm CMOS process. The jitter amplifier with the two-voltage LC buffer occupied 3,300 µm2 and attained 8.4x gain, and that with the single-voltage LC buffer achieved 2.2x gain with an 1,700 µm2 area. The jitter amplification of the sampling clock increased the entropy of a bit stream and improved the results of the NIST test suite so that all the tests passed whereas TRNGs with simple correctors failed. The jitter amplifier attained higher throughput per area than a frequency divider when the required amount of jitter was more than two times larger than the inherent jitter in our test-chip implementations.

This paper proposes a dynamic bandwidth allocation algorithm that improves the network performance and bandwidth sharing efficiency in the upstream channels of a hybrid passive optical network (PON) that combines a fiber-to-the-home (FTTH) access network and wireless sensor networks (WSNs). The algorithm is called the adaptive limited dynamic bandwidth allocation (ALDBA) algorithm. Unlike existing algorithms, the ALDBA algorithm is not limited to controlling just FTTH access networks, it also supports WSNs. For the proposed algorithm, we investigate the difference in the lengths of generated data packets between the FTTH terminals and sensor nodes of WSN to effectively evaluate the end-to-end average packet delay, bandwidth utilization, time jitter, and upstream efficiency. Two variants of the proposed algorithm and a limited service (LS) scheme, which is an existing well-known algorithm, are compared under non-uniform traffic conditions without taking into consideration priority scheduling. We demonstrate the proposed scheme through simulation by generating a realistic network traffic model, called self-similar network traffic. We conducted a detailed simulation using several performance parameters to validate the effectiveness of the proposed scheme. The results of the simulation showed that both ALDBA variants outperformed the existing LS scheme in terms of average packet delay, bandwidth utilization, jitter, and upstream efficiency for both low and high traffic loads.

This paper presents a model to estimate jitter insertion and accumulation in clock repeaters. We propose expressions to estimate, with low computational effort, both static and dynamic clock jitter insertion in repeaters with different sizes, interconnects and slew-rates. It requires only the pre-characterization of a reference repeater, which can be accomplished with a small number of simulations or measurements. Furthermore, we propose expressions for dynamic jitter accumulation that considers the dual nature of power and ground noise impact on delay. The complete model can be used to replace time-consuming transient noise simulations when evaluating jitter in clock distribution systems, and provide valuable insights regarding the impact of design parameters on jitter. Presented results show that our models can estimate jitter insertion and accumulation with an error within 10% of simulation results, for typical designs, and accurately reflect the impact of changing design parameters.

In this paper, using the Linear Time Variant (LTV) phase noise model and considering higher order harmonics generated by the oscillator output signal, a more general formula for transformation of the excess phase to the output signal is presented. Despite the basic LTV model which assumes that the total carrier power is within the fundamental harmonic, in the proposed model, the total carrier power is assumed to be distributed among all output harmonics. For the first harmonic, the developed expressions reduce to the basic LTV formulas. Simulation and experimental results are used to ensure the validity of the model.

This paper proposes a cumulative DNL (CDNL) test methodology for the BIST of ADCs. It analyzes the histogram of the DNL of a predetermined k LSBs distance to determine the DNL and gain error. The advantage of this method over others is that the numbers of required code bins and required samples are significantly reduced. The simulation and measurements of a 12-bit ADC show that the proposed CDNL has an error of less than 5% with only 212 samples, which can only be achieved with 222 samples using the conventional method. It only needs 16 registers to store code bins in this experiment.

This paper investigates a clock frequency generator for ultra-low-voltage sub-picosecond-jitter clock generation in future 0.5-V LSI and power aware LSI. To address the potential possible solution for ultra-low-voltage applications, a 0.5 V clock frequency generator is proposed and implemented. Significant performances, in terms of sub 1-ps jitter, 50 MHz-to-6.4 GHz frequency tuning range with 2 bands and sub 1-mW PDC, demonstrated the viable replacement of ring oscillators in low-voltage and low-jitter clock generator.

This paper investigates the non-data-aided (NDA) carrier frequency estimation of amplitude and phase shift keying (APSK) signals. The true Cramer-Rao bound (CRB) for NDA frequency estimation of APSK signals are derived and evaluated numerically. Characteristic and jitter variance of NDA Luise and Reggiannini (L&R) frequency estimator are analyzed. Verified by Monte Carlo simulations, the analytical results are shown to be accurate for medium-to-high signal-to-noise ratio (SNR) values. Using the proposed closed-form expression, parameters of the algorithm are optimized efficiently to minimize the jitter variance.

To improve simulation precision, the signal model of navigation satellite signal simulators is illustrated, and the generation mechanism and evaluation criteria of an important error source-phase jitter in baseband signal generation, are studied subsequently. An improved baseband signal generator based on dual-ROM look-up table structure is designed with the application of a newly-established concept-virtual sampling rate. Pre-storage of typical baseband signal data and sampling rate conversion adaptive to Doppler frequency shifts are adopted to achieve the high-precision simulation of baseband signals. Performance analysis of the proposed baseband signal generator demonstrates that it can successfully suppress phase jitter and has better spectral performance, generating high-precision baseband signals, which paves the way to improving the overall precision of navigation satellite signal simulators.

As an application of the direct sequence spread spectrum (SS) communication system, there is an M-ary bi-orthogonal SS communication system. In its system, several spreading sequences (bi-orthogonal sequences) are used in a code shift keying basis. Hence, design of the spreading code synchronization system has been an issue in the M-ary bi-orthogonal SS systems. In this paper, the authors focus on a code tracking system using a differential detector and a Delay Lock Loop (DLL). They investigate a tracking performance of their code tracking system by theoretical analysis. In addition, a multi-stage interference canceler is applied to the M-ary bi-orthogonal SS system. As the result, it is shown that the tracking performance of the theoretical analysis is almost the same as that of computer simulations in a multi-user environment. It is also shown that the multi-stage interference canceler is effective in improvement of the BER performance.