The jitter characteristics of synchronous residual time stamp (SRTS) method used in ATM adaptation layer type 1 (AAL1) are analyzed. In this letter, the root mean square amplitude of filtered SRTS jitter is calculated and the computer simulation has been carried out to show jitter of SRTS method considering also the phase time error of network clocks.

This paper presents an explicit analysis of the output error power in wideband sampling systems with finite aperture time in the presence of sampling jitter. Sampling jitter and finite aperture time affect the ability of wideband sampling systems to capture high-frequency signals with high precision. Sampling jitter skews data acquisition timing points, which causes large errors in high-frequency (large slew rate) signal acquisition. Finite sampling-window aperture works as a low pass filter, and hence it degrades the high-frequency performance of sampling systems. In this paper, we discuss these effects explicitly not only in the case that either sampling jitter or finite aperture time exists but also the case that they exist together, for any aperture window function (whose Fourier transform exists) and sampling jitter of Gaussian distribution. These would be useful for the designer of wideband sampling data acquisition systems to know how much sampling jitter and aperture time are tolerable for a specified SNR. Some experimental measurement results as well as simulation results are provided as validation of the analytical results.

For several years, more and more people are joining the Internet and various kind of packets (so called transaction-, block-, and stream-types) have been transmitted in the same network, so that poor network conditions cause loss of the stream-type data packets, such as voices, which request smaller transmission delay time than others. We consider a switching node (router) in a network as an N-series M/G/1-type queueing model and have mainly evaluated the fluctuation of packet delay time and end-to-end delay time, using the two moments matching method with initial value, then define the delay jitter D of a network which consists of jointed N switching nodes. It is clarified that this network is not suitable for voice packets transmission media without measures.

This document analyzes the characteristics of Waiting Time Jitter (WTJ) generated in High-bit-rate Digital Subscriber Lines (HDSL) systems transmitting non-uniform frames. It also derives the Fourier transform of the above WTJ.

An analytic equation was derived for the time jitter of digital NRZ signals due to inter-symbol interference in the PCB transmission lines loaded by DRAM chips which are located in uniform spacing. The inter-symbol interference is caused by a low-pass filtering effect of the loaded transmission line. Good agreements were observed between the equation and measurements with an average error of 17.5%.

In the past, a number of scheduling algorithms that approximate GPS, such as WFQ, have been proposed and have received much attention. This class of algorithms provides per-flow QoS guarantees in terms of the bounded delay and minimum bandwidth guarantee. However, with O(log N) computational cost for each new arrival scheduling, where N is the number of backlogged flows, these algorithms are expensive to implement (e.g., in terms of scalability). Moreover, none of them addresses the issues of delay distribution and jitter. In this paper, we propose a new traffic scheduling discipline called Jitter Control Frame-based Queueing (JCFQ) that provides an upper bound for delay jitter in the case of rate-controlled connections, such as packet video streams and IP telephony, while guaranteeing bounded delay and worst-case fair weighted fairness, such as in the WF2Q algorithm, but with O(1) complexity in selecting the next packet to serve, assuming that the number of flows is fixed. Three different algorithms for slot or service order assignment between flows are proposed: Earliest Jitter Deadline First (EJDF), Rate Monotonic (RM) and Maximum Jitter First (MJF). In these algorithms, delay jitter is formulated into the virtual finish time calculation. We compare the fairness, delay and jitter performance of the JCFQ with that of the MJF algorithm with WF2Q via simulation. The results show that with proper choice of the slot size, JCFQ can achieve better flow isolation in delay distribution than can WF2Q.

A new charge pump is proposed which provides improved jitter characteristics for a phase-locked loop (PLL). The PLL with the proposed charge pump is implemented with 0.6 µm CMOS technology. The measured RMS output jitter is as much as 28% smaller than that of a PLL with a previously reported charge pump structure.

In this paper, we describe statistical properties of timing jitter of symbol timing recovery circuit for carrierless amplitude/phase modulation (CAP)-based very high-rate digital subscriber line (VDSL) system. Analytical expressions of the timing jitter for envelope-based timing recovery system, such as squarer-based timing recovery (S-TR) and absolute-value-based timing recovery (A-TR) schemes, are derived in the presence of additive white Gaussian noise (AWGN) or far-end crosstalk (FEXT). In particular, the analytical and simulation results of the timing jitter performance are presented and compared for a 51.84 Mb/s 16-CAP VDSL system. The A-TR system implemented digitally meets the DAVIC's VDSL system requirement, which specifies the maximum peak-to-peak jitter value of 1.5 nsec and the acquisition time of 20 msec.

This paper describes techniques for widening lock and pull-in ranges and suppressing jitter in clock and data recovery ICs. It is shown theoretically that using a duplicated loop control (DLC)-phase-locked loop (PLL) technique enables wider lock and pull-in ranges in clock and data recovery (CDR) without increasing the cut-off frequency of the jitter transfer function. A 2.5-Gb/s DLC-CDR IC fabricated with a 0.5-µm Si bipolar process provides 2.5 times the lock range and 1.5 times the pull-in range of a conventional CDR IC, and the jitter characteristics of the fabricated CDR IC meet all three STM-16 jitter specifications in ITU-T recommendation G.958.

This paper describes a DLL (Delay Locked Loop) circuit with the mixed-mode phase tuning method. The circuit accomplishes unlimited phase shift and accurate phase alignment through the coarse and fine phase tuning technique. It is based on a dual delay locked loop structure. The main loop is for generating coarsely spaced clocks and the second loop is for fast and accurate phase tuning with digital and analog phase detection. Simulations show that this circuit has 360 degree phase shift capability and can resolve 10 ps phase error using 0.6 µm CMOS technology.

A 160 GHz colliding-pulse mode-locked laser diode (CPM-LD) was stabilized by injection of a stable master laser pulse train repeated at a 16th-subharmonic-frequency (9.873 GHz) of the CPM-LD's mode-locking frequency. Synchroscan steak camera measurements revealed a clear pulse train with 16-times repetition frequency of the master laser pulse train for the stabilized CPM-LD output, indicating that CPM-LD output was synchronized to the master laser and that the timing jitter was also reduced. The timing jitter of the stabilized CPM-LD was quantitatively evaluated by an all-optical down converting technique using the nonlinearity of optical fiber. This technique is simple and has a wider bandwidth in comparison to a conventional technique, making it possible to accurately measure the phase noise of ultrafast optical pulse train when its repetition frequency exceeds 100 GHz. The electrical power spectra measurements indicated that the CPM-LD's mode-locking frequency was exactly locked by the injection of the master laser pulse train and that the timing jitter decreased as the injection power increased. The timing jitter was reduced from 2.2 ps in free running operation to 0.26 ps at an injection power of 57 mW, comparable to that of the master laser (0.21 ps).

This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.

This paper describes a jitter suppression technique for a clock multiplier IC that uses a phase-locked loop (PLL). It is shown that the jitter cutoff frequency of the jitter transfer function can be greatly improved by adding a surface acoustic wave (SAW) filter whose center frequency equals the input frequency. The jitter transfer function is mainly determined by the characteristics of the SAW filter. Therefore, the clock multiplier IC can be set at a high loop gain to minimize the jitter generation without increasing the jitter cutoff frequency. The use of a clock multiplier IC that was fabricated with Si bipolar technology and a SAW filter with the center frequency of 155.52 MHz and a quality (Q) factor of 1500 results in a very low jitter generation of 3.5 mUI rms and an extremely low jitter cutoff frequency of about 50 kHz when the clock multiplier converts a clock frequency of 155.52 MHz into a 2.48832-GHz signal.

The additive noise response of a charge pump phase-locked loop in the synchronous mode of operation has been studied. In order to determine the tracking and noise performances of the loop, mean square values of tracking error and local oscillator phase jitter have been analytically obtained. Analytical results agree well with the simulation results obtained here and elsewhere. The analysis performed can be used in choosing different system parameters for optimum system operation.

One of the limitation factors on the achievable distance for long-haul nonlinear Return-to-Zero (RZ)-Gaussian pulse transmission on optical fiber links is timing jitter. Although it is well known that the dispersion management technique is very effective to reduce the timing jitter, comparisons among some dispersion management methods based on the timing jitter reduction have not been reported yet. In this paper, timing jitter reduction by some dispersion management methods in nonlinear RZ-Gaussian pulse transmission systems are discussed. Moreover, we will report that the amount of timing jitter at the receiver side drastically changes depending on the configuration of dispersion managed optical fiber transmission line.

For the reduction of the jitter originated from the cell losses in ATM network when CBR traffic is transferred on AAL5, we propose that the receiver maintain a timer whose expiration time is proportional to the cell time of the source traffic plus the standard deviation of the 1-point CDV of the received ATM cells. Moreover, to enhance the granularity of the error or loss detection mechanism in the AAL5 PDUs, we also modified the AAL5 PDU trailer fields so that each cell comprising the AAL5 PDU has a sequence number field. The simulation results show that the peak-to-peak PDV of the AAL5 PDU by the proposed method is less than 69.4% to that by AAL5. Moreover, the AAL5 user receives the same or more error-free transport packets in the proposed algorithm than those in the ITU-T AAL5 for the same network simulation environment.

This paper describes a wide-frequency-range phase-locked-loop (PLL) clock generator embedded in a gate array LSI using 0.25 µm CMOS/SIMOX technology. The four ratios of internal clock frequency to external clock frequency this generator supports are 2, 4, 8, and 16. The PLL has two kinds of voltage-controlled oscillators that are selected automatically according to the frequency so as to widen the operating frequency range while keeping jitter low. Measured results show that the PLL operates with a lock range from 5 to 500 MHz. At 500 MHz, the peak-to-peak jitter is 50 ps. The supply voltage is 2 V and power dissipation is less than 14 mW. At a supply voltage of 2 V, the maximum operating frequency of 0.25 µm CMOS/SIMOX PLL is 30% higher than that of 0.25 µm bulk CMOS PLL.

We have developed a new type of phase interpolation direct digital synthesizer (DDS) with a symmetrically structured delay generator. The new DDS is similar to a sine output DDS in that it produces lower spurious signals, but it does not require a sine look-up table. The symmetrically structured delay generator reduces the periodic jitter in the most significant bit (MSB) of the DDS accumulator. The symmetrical structure enables the delay generator to produce highly accurate delay timing and eliminates the need to adjust the circuit constants. Experimental results confirm frequency synthesizer operation in which the spurious signal level is reduced to less than that of the accumulator.

In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10-11 BER, 8 times oversampling has about 2 dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits depending on the input data rate and input noise. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5 dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling in white noise dominant input data. The results were applied to the fabricated circuits to validate the analysis.

Since the inception of optical networking, a goal has been to create an all-optical network. The rapid breakthrough for WDM in point to point links has brought this prospect considerably closer, however, at the same time, questions regarding the scalability of the all-optical network remain. In this paper, we review our recent research in this area, partly performed within the European Union project METON (METropolitan Optical Network), and discuss the all-optical approach and different optoelectronic alternatives, mainly of the 2R (reamplify and reshape) type.