We have developed a new type of phase interpolation direct digital synthesizer (DDS) with a symmetrically structured delay generator. The new DDS is similar to a sine output DDS in that it produces lower spurious signals, but it does not require a sine look-up table. The symmetrically structured delay generator reduces the periodic jitter in the most significant bit (MSB) of the DDS accumulator. The symmetrical structure enables the delay generator to produce highly accurate delay timing and eliminates the need to adjust the circuit constants. Experimental results confirm frequency synthesizer operation in which the spurious signal level is reduced to less than that of the accumulator.

A 3-bit flash analog-to-digital converter (ADC) for electronic dispersion compensation (EDC) was developed using InP HBTs. Nyquist operation was confirmed up to 24 Gsps, which enables oversampling acquisition for 10 Gbit/s non-return-to-zero (NRZ) signals. The ADC can also be operated at up to 37 Gsps for low input frequencies. To reduce aperture jitter and achieve a wide band of over 7 GHz, an analog input signal for all pre-amplifiers and a clock signal for all latched comparators are provided as traveling waves through coplanar transmission lines. EDC was demonstrated by capturing a 10-Gbit/s pseudo-random bit stream (PRBS) with the waveform degraded by polarization-mode dispersion (PMD). By using the captured data, we confirmed that a calculation of a transversal filter mitigates PMD.

This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/-0.07 LSB and +0.27/-0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24 GS/s are also obtained. The total power consumption is as low as 0.88 W with a supply voltage of -4.0 V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5 bits or more.

A summer-embedded sense amplifier (SE SA) is proposed to reduce feedback loop delay (TFB) in a decision feedback equalizer (DFE). In the SE SA, the position of the ISI compensator is changed from the latch input to the latch output, and hence the TFB is reduced. The simulated DFE achieves 32Gb/s and 66fJ/b with a 1-V 65-nm CMOS process.

This paper presents a design of CMOS transimpedance amplifier (TIA) and peaking inductor for high speed, low power and small area. To realize high density integration of optical I/O, area reduction is an important figure as well as bandwidth, power and so on. To determine design parameters of multi-stage inverter-type TIA (INV-TIA) with peaking inductors, we derive a simplified model of the bandwidth and the energy per bit. Multi-layered on-chip inductors are designed for area-effective inductive peaking. A 5-stage INV-TIA with 3 peaking inductors is fabricated in a 65-nm CMOS. By using multi-layered inductors, 0.02 mm2 area is achieved. Measurement results show 45 Gb/s operation with 49 dBΩ transimpedance gain and 4.4 mW power consumption. The TIA achieves 98 fJ/bit energy efficiency.

We have developed a new type of phase interpolation DDS with a digitally controlled delay generator. The new DDS is similar to a sine output DDS in that it produces low spurious signals, but it does not require a sine look-up table. Periodic jitter in the MSB of the DDS accumulator is reduced with the digitally controlled delay generator. Experimental results confirm successful frequency synthesizer operation in which the spurious signal level is successfully reduced to less than that the MSB of the accumulator.

We propose a new phase interpolator that provides precise fractional phase pulses without the need to adjust circuit constants. The variable phases are produced by detecting the coincidence of two voltages, the ramp wave and the threshold voltage. The new phase interpolator can keep the same ramp wave slope and the same threshold voltage for different output phases. This significantly reduces the power dissipation of the voltage comparator. This phase interpolator can be applied to various timing circuits and clock generators, such as frequency multipliers and direct digital synthesizers. We present a novel frequency doubler, a novel frequency tripler, a direct digital synthesizer (DDS), and a novel wideband DDS (WDDS) as applications of our new phase interpolator, which uses 0.35-mm CMOS process technology. Experimental results confirm the functionarity of the new phase interpolator. An 8-bit complete DDS IC dissipates only 2.1 mA at a 50-MHz clock rate and a supply voltage of 2.8 V.

A design scheme for a high-speed differential-input limiting transimpedance amplifier (TIA) was developed. The output-stage amplifier of the TIA is investigated in detail in order to suppress undershoot and ringing in the output waveform. The amplifier also includes a peak detector for the received signal strength indicator (RSSI) output, which is used to control the optical demodulator for differential-phase-shift-keying or differential-quadrature-phase-shift-keying formats. The limiting TIA was fabricated on the basis of 1-µm emitter-width InP-based heterojunction-bipolar-transistor (HBT) IC technology. Its differential gain is 39 dB, its 3-dB bandwidth is 27 GHz, and its estimated differential transimpedance gain is 73 dBΩ. The obtained output waveform shows that the developed design scheme is effective for suppressing undershoot and ringing.