IEICE TRANSACTIONS on Electronics
A 24-GS/s 6-bit R-2R Current-Steering DAC in InP HBT Technology
Summary :
This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/-0.07 LSB and +0.27/-0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24 GS/s are also obtained. The total power consumption is as low as 0.88 W with a supply voltage of -4.0 V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5 bits or more.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E93-C No.8 pp.1279-1285
- Publication Date
- 2010/08/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E93.C.1279
- Type of Manuscript
- Special Section PAPER (Special Section on Heterostructure Microelectronics with TWHM 2009)
- Category
- III-V High-Speed Devices and Circuits
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Munehiko NAGATANI, Hideyuki NOSAKA, Shogo YAMANAKA, Kimikazu SANO, Koichi MURATA, "A 24-GS/s 6-bit R-2R Current-Steering DAC in InP HBT Technology" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 8, pp. 1279-1285, August 2010, doi: 10.1587/transele.E93.C.1279.
Abstract: This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/-0.07 LSB and +0.27/-0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24 GS/s are also obtained. The total power consumption is as low as 0.88 W with a supply voltage of -4.0 V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5 bits or more.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1279/_p
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@ARTICLE{e93-c_8_1279,
author={Munehiko NAGATANI, Hideyuki NOSAKA, Shogo YAMANAKA, Kimikazu SANO, Koichi MURATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 24-GS/s 6-bit R-2R Current-Steering DAC in InP HBT Technology},
year={2010},
volume={E93-C},
number={8},
pages={1279-1285},
abstract={This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/-0.07 LSB and +0.27/-0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24 GS/s are also obtained. The total power consumption is as low as 0.88 W with a supply voltage of -4.0 V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5 bits or more.},
keywords={},
doi={10.1587/transele.E93.C.1279},
ISSN={1745-1353},
month={August},}
Copy
TY - JOUR
TI - A 24-GS/s 6-bit R-2R Current-Steering DAC in InP HBT Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 1279
EP - 1285
AU - Munehiko NAGATANI
AU - Hideyuki NOSAKA
AU - Shogo YAMANAKA
AU - Kimikazu SANO
AU - Koichi MURATA
PY - 2010
DO - 10.1587/transele.E93.C.1279
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2010
AB - This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/-0.07 LSB and +0.27/-0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24 GS/s are also obtained. The total power consumption is as low as 0.88 W with a supply voltage of -4.0 V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5 bits or more.
ER -
English
