The clock recovery circuit is a key component in high-speed electrical time-division multiplexing (ETDM) transmission systems. In the case of clock extraction from non-return-to-zero (NRZ) signals, differentiation and full-wave rectification are indispensable. Exclusive OR/NOR circuits (XOR) are widely used for this purpose. In this paper, we describe an XOR IC fabricated with 0. 1-µm gate-length InAlAs/InGaAs/InP HEMTs for a 40-Gbit/s class clock recovery circuit. The IC was configured with a symmetrical Gilbert cell type XOR gate and two types of peaking techniques are used to achieve its high bit-rate. On-wafer-measurements indicate that the IC operates as fast as 80 Gbit/s and can extract a 40-GHz frequency component from 40-Gbit/s NRZ input signals. To confirm the feasibility of using the packaged XOR IC in clock recovery circuits, the conversion gain of the IC, which was operated as a differentiater and full-wave rectifier, was evaluated. Assuming that the input to the clock recovery circuit is a 1 Vp-p signal, the relatively high output power of -17 dBm can be obtained with low dependency on the length of the input pseudo-random bit streams. Furthermore, a clock recovery circuit was assembled using the packaged XOR IC, a waveguide filter and a commercial amplifier; it offers the practical system-bit-rate of 39. 81312 GHz with the low rms jitter of 900 fs.

An ultra-fast optoelectronic decision circuit using resonant tunneling diodes (RTD's) and a uni-traveling-carrier photodiode (UTC-PD) is proposed. The circuit employs two cascaded RTD's for ultra-fast logic operation and one UTC-PD that offers a direct optical input interface. This novel configuration is suitable for ultra-fast decision operation. Two types of decision circuits are introduced: a positive-logic type and a negative-logic type. Operations of these circuits were simulated using SPICE with precisely investigated RTD and UTC-PD models. In terms of circuit speed, 40-Gbit/s decision and 80-Gbit/s demultiplexing were expected. Furthermore, the superiority of the negative-logic type in terms of the circuit operating margin and the relationship between input peak photocurrent and effective logic swing were clarified by SPICE simulations. In order to confirm the basic functions of the circuits and the accuracy of the simulations, circuits were fabricated by monolithically integrating InP-based RTD's and UTC-PD's. The circuits successfully exhibited 40-Gbit/s decision operation and 80-Gbit/s demultiplexing operation with less than 10-mW power dissipation. The superiority of the negative-logic type circuit for the circuit operation was confirmed, and the relationship between the input peak photocurrent and the effective logic swing was as predicted.

Phase-inversion between neighboring pulses appearing in carrier-suppressed return-to-zero pulses is effective in reducing the signal distortion due to chromatic dispersion and nonlinear effects. A generation method of the anti-phase pulses at 40 GHz is demonstrated by using semiconductor mode-locked lasers integrated with chirped gratings. Operation principle and pulse characteristics are described. Suppression of pulse distortion due to fiber dispersion is confirmed for generated anti-phase pulses. Repeaterless 150-km dispersion-shifted-fiber L-band transmission at 42.7 Gbit/s is demonstrated by using the pulse source.

We experimentally studied the polarization mode dispersion (PMD) tolerance of an feed-forward equalizer (FFE) electronic dispersion compensation (EDC) IC in the absence of adaptive control, in 43-Gbit/s RZ-DQPSK transmission. Using a 3-tap FFE IC composed of InP HBTs, differential group delay (DGD) tolerance at a 2-dB Q penalty is shown to be extended from 25 ps to up to 29 ps. When a polarization scrambler is used, the tolerance is further extended to 31 ps. This value is close to the tolerance obtained with adaptive control, without a polarization scrambler.

This paper proposes a parallel word alignment procedure for m Binary with 1 Complement Insertion (mBlC) or Differential m Binary with l Mark Insertion (DmBlM) line code. In the proposed procedure for mBlC line code, the word alignment circuit searches (m+1) bit pairs in parallel for complementary relationships. A Signal Flow Graph Model for the parallel word alignment procedure is also proposed, and its performance attributes are numerically analyzed. The attributes are compared with those of the conventional bit-by-bit procedure, and it is shown that the proposed procedure displays superior performance in terms of False-Alignment Probability and Maximum Average Aligning Time. The proposed procedure is suitable for high speed optical data links, because it can be easily implemented using a parallel signal processor operating at a clock rate equal to 1/(m+1) times the mBlC line rate.

An SCFL-compatible 40-Gbit/s selector circuit using resonant tunneling diodes (RTDs) and high-electron-mobility transistors (HEMTs) is presented. The circuit comprises two monostable-bistable transition elements (MOBILEs) using RTDs, a HEMT NOR circuit, and a HEMT output buffer based on source-coupled-FET logic (SCFL). The circuit is fabricated by monolithically integrating RTDs and 0.1-µm HEMTs on an InP substrate. The fabricated circuit exhibits clear eye-opening at 40 Gbit/s with an output swing of 800 mVp-p, which is close to the conventional high-speed logic IC interface called SCFL.

We study effects of preamplifier nonlinearity on polarization mode dispersion (PMD) equalization performance of feed-forward equalizer (FFE) electronic dispersion compensation (EDC) IC. We have shown that a nonlinear limiting amplifier can be used as a preamplifier for FFE EDC IC for a 6-dB dynamic range.

A clock recovery circuit is a key component in optical communication systems. In this paper, an optoelectronic clock recovery circuit is reported that monolithically integrates a resonant tunneling diode (RTD) and a uni-traveling-carrier photodiode (UTC-PD). The circuit is an injection-locked-type RTD oscillator that uses the photo-current generated by the UTC-PD. Fundamental and sub-harmonic clock extraction is confirmed for the first time with good clock recovery circuit characteristics. The IC extracts an electrical 11.55-GHz clock signal from 11.55-Gbit/s RZ optical data streams with the wide locking range of 450 MHz and low power dissipation of 1.3 mW. Furthermore, the extraction of a sub-harmonic clock from 23.1-Gbit/s and 46.2-Gbit/s input data streams is also confirmed in the wider locking range of 600 MHz. The RMS jitter as determined from a single sideband phase noise measurement is extremely low at less than 200 fs in both cases of clock and sub-harmonic clock extraction. To our knowledge, the product of the output power and operating frequency of the circuit is the highest ever reported for injection-locked-type RTD oscillators. These characteristics indicate the feasibility of the optoelectronic clock recovery circuit for use in future ultra-high-speed fully monolithic receivers.

A 50-Gbit/s demultiplexer IC module that uses 0.1-µm InAlAs/InGaAs/InP HEMTs is reported. The maximum error-free operation bit-rate of a fabricated module is 50 Gbit/s, and a wide phase margin of 170 degrees is obtained at 43 Gbit/s. 50-Gbit/s demultiplexing is the fastest performance of all packaged demultiplexer ICs yet reported.

This letter reports a high-sensitivity GaAs decision IC for ultra-high-speed optical transmission systems. The IC was designed using LSCFL (Low-power Source Coupled FET Logic) and fabricated with 0.2-µm-gate-length MESFETs with a cut-off frequency of 50GHz. The input voltage sensitivity was 35mV at 10Gbit/s. This is the highest sensitivity ever reported for a MESFET decision IC.

This paper describes IC-oriented high-performance AlGaAs/GaAs heterojunction bipolar transistors that were fabricated to demonstrate their great potential in applications to high-speed integrated circuits. A collector structure of ballistic collection transistors with a launcher (LBCTs) shortens the intrinsic delay time of the transistors. A novel and simple self-aligned fabrication process, which features an base-metal-overlaid structure (BMO), reduces emitter- and base-resistances and collector capacitance. The combination of the thin-collector LBCT layer structure and the BMO self-alignment technology raises the average value of cutoff frequency, fT, to 160 GHz with a standard deviation as small as 4.3 GHz. By modifying collector thickness and using Pt/Ti/Pt/Au as the base ohmic contact metal in BMO-LBCTs, the maximum oscillation frequency, fmax, reaches 148 GHz with a 114 GHz fT. A 2:1 multiplexer with retiming D-type flip-flops (DFFs) at input/output stages fabricated on a wafer with the thin-collector LBCT structure operates at 19 Gbit/s. A monolithic preamplifier fabricated on the same wafer has a transimpedance of 52 dBΩ with a 3-dB-down bandwidth of 18.5 GHz and a gain S21 OF 21 dB with a 3-dB-down bandwidth of 19 GHz. Finally, a 40 Gbit/s selector IC and a 50 GHz dynamic frequency divider that were successfully fabricated using the 148-GHz fmax technologies are described.

The authors report ultra-high-speed digital IC modules that use 0.1-µm InAlAs/InGaAs/InP HEMTs for broadband optical fiber communication systems. The multiplexer IC module operated at up to 70 Gbit/s, and error-free operation of the decision IC module was confirmed at 50 Gbit/s. The speed of each module is the fastest yet reported for its kind.

This paper describes a new multiple DmB1C (Differential m Binary 1 Complement insertion) /DmB1M (Differential m Binary with 1 Mark insertion) coding scheme for high-speed optical multiplex transmission. The coding scheme has the characteristics of small consecutive identical digits and a good balance between marks and spaces. Furthermore, it has also good synchronization characteristics and higher flexibility for extension to high capacity transmission than the conventional mB1C or DmB1M coding schemes. We describe a design methodology for a multiplex transmission system using the proposed coding scheme, and verify the characteristics of the proposed coding scheme using an experimental setup of a 2.8 Gbit/s serial optical interconnection circuit, which has 16 parallel 156 Mbit/s inputs. The coding scheme realizes transmission systems with simple analog circuit configuration, and small digital circuit complexity with wide dynamic range and good mark ratio tolerance.

This paper presents a 120-GHz-band amplifier module with a hermetic sealing structure for a broadband wireless system. The sealing structure for F-band waveguides is a laminate composed of two sealing plates and a spacer. Each sealing plate has a fused glass window and separates inside air from the ambient atmosphere. The design process of the sealing structure is simple and has good simulation fidelity. The hermetic sealing structure designed for an amplifier in a 120-GHz-band wireless link has an insertion loss of less than 1dB and a return loss of more than 15dB in the operating band. We made three kinds of sealed modules to evaluate the sealing function. The modules sealed with this technique meet the hermetic-seal standard in MIL-STD-883F. We then verified that the sealing structure on the sealed modules has a small enough effect for the transmittance of the intrinsic characteristics. In addition, we performed 10-Gbit/s data transmission using a sealed amplifier module with the bit error rate of less than 10-10.

A design scheme for a high-speed differential-input limiting transimpedance amplifier (TIA) was developed. The output-stage amplifier of the TIA is investigated in detail in order to suppress undershoot and ringing in the output waveform. The amplifier also includes a peak detector for the received signal strength indicator (RSSI) output, which is used to control the optical demodulator for differential-phase-shift-keying or differential-quadrature-phase-shift-keying formats. The limiting TIA was fabricated on the basis of 1-µm emitter-width InP-based heterojunction-bipolar-transistor (HBT) IC technology. Its differential gain is 39 dB, its 3-dB bandwidth is 27 GHz, and its estimated differential transimpedance gain is 73 dBΩ. The obtained output waveform shows that the developed design scheme is effective for suppressing undershoot and ringing.

The authors report on a 40-Gbit/s superdynamic decision IC fabricated with 0.12-µm GaAs MESFETs. The key to attaining high-speed decision IC is not only high-speed flip-flop circuits but also wideband input and output buffer circuits. 40 Gbit/s is the fastest operating speed of decision ICs fabricated with GaAs MESFETs.

This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/-0.07 LSB and +0.27/-0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24 GS/s are also obtained. The total power consumption is as low as 0.88 W with a supply voltage of -4.0 V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5 bits or more.

A clock recovery circuit is a key component in optical communication systems. In this paper, an optoelectronic clock recovery circuit is reported that monolithically integrates a resonant tunneling diode (RTD) and a uni-traveling-carrier photodiode (UTC-PD). The circuit is an injection-locked-type RTD oscillator that uses the photo-current generated by the UTC-PD. Fundamental and sub-harmonic clock extraction is confirmed for the first time with good clock recovery circuit characteristics. The IC extracts an electrical 11.55-GHz clock signal from 11.55-Gbit/s RZ optical data streams with the wide locking range of 450 MHz and low power dissipation of 1.3 mW. Furthermore, the extraction of a sub-harmonic clock from 23.1-Gbit/s and 46.2-Gbit/s input data streams is also confirmed in the wider locking range of 600 MHz. The RMS jitter as determined from a single sideband phase noise measurement is extremely low at less than 200 fs in both cases of clock and sub-harmonic clock extraction. To our knowledge, the product of the output power and operating frequency of the circuit is the highest ever reported for injection-locked-type RTD oscillators. These characteristics indicate the feasibility of the optoelectronic clock recovery circuit for use in future ultra-high-speed fully monolithic receivers.

This paper is a report on a high ESD breakdown-voltage InP HBT transimpedance amplifier IC for optical video distribution systems. To make ESD breakdown-voltage higher, we designed ESD protection circuits integrated in the TIA IC using base-collector/base-emitter diodes of InP HBTs and resistors. These components for ESD protection circuits have already existed in the employed InP HBT IC process, so no process modifications were needed. Furthermore, to meet requirements for use in optical video distribution systems, we studied circuit design techniques to obtain a good input-output linearity and a low-noise characteristic. Fabricated InP HBT TIA IC exhibited high human-body-model ESD breakdown voltages (±1000 V for power supply terminals, ±200 V for high-speed input/output terminals), good input-output linearity (less than 2.9-% duty-cycle-distortion), and low noise characteristic (10.7 pA/ averaged input-referred noise current density) with a -3-dB-down higher frequency of 6.9 GHz. To the best of our knowledge, this paper is the first literature describing InP ICs with high ESD-breakdown voltages.

In order to develop high-speed ICs, it is important to clarify the relationship between circuit speed and device parameters. An analytical expression for circuit performance is effective for this purpose. This paper describes an analytical toggle frequency expression for Source-Coupled FET Logic (SCFL) frequency dividers. The proposed equation is expressed as the sum of the product of sensitivity coefficients of FET parameters and time constants which are extracted through a small signal transfer function analysis. These sensitivity coefficients are extracted using SPICE simulations. The equation is a simple formula with only five coefficients, which is much smaller than conventional sensitivity analyses. Furthermore, the accuracy of the proposed equation is improved compared to an analytical method based on the small signal transfer function which we previously proposed. The equation can be easily extended to consider interconnection delay time. The calculated maximum toggle frequencies using the equation show good agreement with SPICE simulations and experimental results for a wide gate-length variation range of 0. 12-µm to 0. 24-µm GaAs MESFETs. By re-extraction of another set of sensitivity coefficients, the proposed equation can be widely applied to shorter gate-length GaAs MESFETs and other FET devices such as HEMT devices. The expression clearly shows the relationship between the circuit performance and intrinsic FET parameters. According to the equation, the key parameters for high-speed circuit operation are high transconductance with a low drain conductance, and a low gate-drain capacitance. The equation can be used as a criterion for the optimization of the FET structure to realize high speed circuit performance.