This paper proposes the assignment of resource blocks (RBs) to reduce the peak-to-average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) in a multi-user OFDM system. This system ranks the users according to the channel state information (CSI) for RB assignment. In our proposed technique, an RB is assigned to either the first- or second-ranked mobile station (MS) to minimize the PAPR of the OFDM signal. While this process reduces the PAPR, the throughput is also reduced because of the user diversity gain loss. A PAPR-throughput tradeoff is then established. Theoretical analyses and computer simulations confirm that when the number of MSs becomes large, the PAPR-throughput tradeoff is eased because of the minimal effect of the diversity gain loss. Therefore, significant PAPR reduction is achieved with only a slight degradation in the throughput.

Interleaved Frequency Division Multiple Access (IFDMA) is a modulation scheme that achieves a frequency diversity gain and establishes a frequency orthogonal channel. In multicarrier modulation schemes such as orthogonal frequency division multiplexing (OFDM), a pilot signal is dispersed over the frequency and time domains and thus the estimated channel transfer function can track the fluctuations that occur in the time and frequency domains. This pilot signal is referred to as a scattered pilot signal. However, the scattered pilot signal has not yet been applied to IFDMA. In this paper, we propose a scattered pilot signal for IFDMA. The problem with the proposed scattered pilot signal is that it increases the peak to average power ratio of the transmitted signal. Therefore, we also propose three peak-to-average power ratio (PAPR) reduction schemes for the IFDMA symbols including the scattered pilot signal. A computer simulation shows that the proposed pilot signal achieves a highly accurate channel estimation under various channel conditions and that the proposed reduction shemes significantly reduce the PAPR.

In this paper, a scheme for constructing the flat frequency spectrum of interleaved frequency division multiple access (IFDMA) is proposed. Since IFDMA is one of the single carrier modulation schemes, the frequency spectrum components are fluctuated and depend on the information data sequence. Even if IFDMA modulation scheme makes frequency spectrum dispersive for obtaining frequency diversity gain, frequency diversity gain is reduced by the fluctuation of frequency spectrum. In addition, in decision directed channel estimation (DDCE), which achieves good channel estimation accuracy in fast fading environment, the accuracy of channel transfer function estimated at the significant attenuated frequency component is much degraded. In the proposed technique, a random phase sequence is multiplied to the information data sequence for constructing the flat frequency spectrum. As a result, the frequency diversity gain is enlarged and the accuracy of channel estimation by DDCE is improved. Furthermore, we consider the blind estimation technique for the random phase sequence selected by transmitter. We show the effects of the proposed scheme by computer simulation.

This paper presents the technologies for over-40-Gbit/s operation of InP-based HEMT ICs for future optical communication systems. High-speed interconnection using low-permittivity benzocyclobutene (BCB) film as an inter-layer insulator decreases interconnection delay and results in high-speed operation of digital circuits. A static frequency divider and a 2 : 1 multiplexer using this novel interconnection demonstrate 49-GHz and 80-Gbit/s operation, respectively. Ultrahigh-speed digital/analog ICs fabricated using the HEMTs were used in 40 Gbit/s optical transmission experiment and showed good bit-error-rate performance. A novel two-step recess process for gate recess etching considerably improves the performance of InP-based HEMTs and is found to be promising for future ultrashort-gate devices.

The clock recovery circuit is a key component in high-speed electrical time-division multiplexing (ETDM) transmission systems. In the case of clock extraction from non-return-to-zero (NRZ) signals, differentiation and full-wave rectification are indispensable. Exclusive OR/NOR circuits (XOR) are widely used for this purpose. In this paper, we describe an XOR IC fabricated with 0. 1-µm gate-length InAlAs/InGaAs/InP HEMTs for a 40-Gbit/s class clock recovery circuit. The IC was configured with a symmetrical Gilbert cell type XOR gate and two types of peaking techniques are used to achieve its high bit-rate. On-wafer-measurements indicate that the IC operates as fast as 80 Gbit/s and can extract a 40-GHz frequency component from 40-Gbit/s NRZ input signals. To confirm the feasibility of using the packaged XOR IC in clock recovery circuits, the conversion gain of the IC, which was operated as a differentiater and full-wave rectifier, was evaluated. Assuming that the input to the clock recovery circuit is a 1 Vp-p signal, the relatively high output power of -17 dBm can be obtained with low dependency on the length of the input pseudo-random bit streams. Furthermore, a clock recovery circuit was assembled using the packaged XOR IC, a waveguide filter and a commercial amplifier; it offers the practical system-bit-rate of 39. 81312 GHz with the low rms jitter of 900 fs.

49-GHz operation for a state-of-the-art static frequency divider using FETs is achieved with high-performance 0.1-µm-gate InAlAs/InGaAs/InP HEMTs and high-speed double-layer interconnections with a thick low-permittivity BCB inter-layer dielectric film. An experiment shows that the propagation delay for the upper-layer line in the double-layer interconnections is less than half of that for the conventional single-layer interconnections directly on InP-substrate. The frequency divider with the double-layer interconnections is about 20% faster than the conventional one with the single-layer interconnections. A delay time analysis reveals that this speed increase is due to the decrease in interconnection propagation delay.

Noise characteristics of InAlAs/InGaAs HEMT's passivated by SiN are investigated to ascertain their suitability for practical applications in circuit such as MMIC's. A 0.18-µm-gate-length device with 125-µm-gate width and 8-gate fingers showed the lowest minimum noise figure of 0.43 dB at 26 GHz with an associated gain of 8.5 dB of any passivated device ever reported. This value is also comparable to the lowest reported minimum noise figure obtained by bare InAlAs/InGaAs HEMT's in spite of increased parasitic capacitances due to the SiN passivation. Thes excellent noise performance was achieved by employing non-alloyed ohmic contact, a T-shaped gate geometry and a multi-finger gate pattern. To reduce the contact resistance of the non-alloyed ohmic contact, a novel n+-InGaAs/n+-InAlAs cap layer was used resulting in a very low contact resistance of 0.09 Ωmm and a low sheet resistance for all layers of 145 Ω/sq. No increase in these resistances was observed after SiN passivation, and a very low source resistance of 0.16 Ωmm was obtained. An analysis of equivalent circuit parameters revealed that the T-shaped gate and multi-finger gate pattern drastically decrease gate resistance.

Two novel frequency rotation techniques that suppress multipath interference and increase the frequency diversity gain are proposed for uplink IFDMA systems. These benefits are especially important as the performance of traditional IFDMA falls significantly when the number of simultaneous accessing users becomes large. Frequency rotation was originally proposed to suppress the multipath interference and enlarge the frequency diversity gain of downlink access. Unfortunately, it cannot be applied to the uplink due to the loss of orthogonality among users in the frequency domain. In the proposed frequency rotation techniques, users do not share the multiple frequency orthogonal channels and thus orthogonality among users is maintained. The proposed technique is verified by computer simulations.

This paper presents a compact fully-differential distributed amplifier using a coupled inductor. Differential distributed amplifiers are widely required in optical communication systems. Most of the distributed amplifiers reported in the past are single-ended or pseudo-differential topologies. In addition, the differential distributed amplifiers require many inductors, which increases the silicon cost. In this study, we use differentially coupled inductors to reduce the chip area to less than half and eliminate the difficulties in layout design. The challenge in using coupled inductors is the capacitive parasitic coupling that degrades the flatness of frequency response. To address this challenge, the odd-mode image parameters of a differential artificial transmission line are derived using a simple loss-less model. Based on the analytical results, we optimize the dimensions of the inductor with the gradient descent algorithm to achieve accurate impedance matching and phase matching. The amplifier was fabricated in 0.18-µm CMOS technology. The core area of the amplifier is 0.27 mm2, which is 57% smaller than the previous work. Besides, we demonstrated a small group delay variation of ±2.7 ps thanks to the optimization. the amplifier successfully performed 30-Gbps NRZ and PAM4 transmissions with superior jitter performance. The proposed technique will promote the high-density integration of differential traveling wave devices.