A novel delta-sigma modulator that utilizes a resonant-tunneling diode (RTD) quantizer is proposed and its operation is investigated by HSPICE simulations. In order to eliminate the signal-to-noise-and-distortion ratio (SINAD) degradation caused from the poor isolation of a single-stage quantizer (1SQ), a three-stage quantizer (3SQ), which consists of three cascoded RTD quantizers, is introduced. At a sample rate of 10 Gsps (samples per a second) and a signal bandwidth of 40 MHz (oversampling ratio of 128), the modulator demonstrates a SINAD of 56 dB, which corresponds to the effective number of bits of 9.3.

This paper presents the technologies for over-40-Gbit/s operation of InP-based HEMT ICs for future optical communication systems. High-speed interconnection using low-permittivity benzocyclobutene (BCB) film as an inter-layer insulator decreases interconnection delay and results in high-speed operation of digital circuits. A static frequency divider and a 2 : 1 multiplexer using this novel interconnection demonstrate 49-GHz and 80-Gbit/s operation, respectively. Ultrahigh-speed digital/analog ICs fabricated using the HEMTs were used in 40 Gbit/s optical transmission experiment and showed good bit-error-rate performance. A novel two-step recess process for gate recess etching considerably improves the performance of InP-based HEMTs and is found to be promising for future ultrashort-gate devices.

We demonstrated the uniformity and stability as well as the high breakdown voltage of 0.1-µm-gate InP HEMTs with a double recess structure. To overcome the drawbacks regarding the uniformity and stability in the double recess structure, an InP passivation layer that functions as an etch-stopper and a surface passivator was successfully applied to the structure. It was confirmed that there was no degradation in the uniformity and stability of device performance for the double recess HEMTs that had the breakdown voltages in the on-state and off-state improved by a factor of 1.6.

The clock recovery circuit is a key component in high-speed electrical time-division multiplexing (ETDM) transmission systems. In the case of clock extraction from non-return-to-zero (NRZ) signals, differentiation and full-wave rectification are indispensable. Exclusive OR/NOR circuits (XOR) are widely used for this purpose. In this paper, we describe an XOR IC fabricated with 0. 1-µm gate-length InAlAs/InGaAs/InP HEMTs for a 40-Gbit/s class clock recovery circuit. The IC was configured with a symmetrical Gilbert cell type XOR gate and two types of peaking techniques are used to achieve its high bit-rate. On-wafer-measurements indicate that the IC operates as fast as 80 Gbit/s and can extract a 40-GHz frequency component from 40-Gbit/s NRZ input signals. To confirm the feasibility of using the packaged XOR IC in clock recovery circuits, the conversion gain of the IC, which was operated as a differentiater and full-wave rectifier, was evaluated. Assuming that the input to the clock recovery circuit is a 1 Vp-p signal, the relatively high output power of -17 dBm can be obtained with low dependency on the length of the input pseudo-random bit streams. Furthermore, a clock recovery circuit was assembled using the packaged XOR IC, a waveguide filter and a commercial amplifier; it offers the practical system-bit-rate of 39. 81312 GHz with the low rms jitter of 900 fs.

49-GHz operation for a state-of-the-art static frequency divider using FETs is achieved with high-performance 0.1-µm-gate InAlAs/InGaAs/InP HEMTs and high-speed double-layer interconnections with a thick low-permittivity BCB inter-layer dielectric film. An experiment shows that the propagation delay for the upper-layer line in the double-layer interconnections is less than half of that for the conventional single-layer interconnections directly on InP-substrate. The frequency divider with the double-layer interconnections is about 20% faster than the conventional one with the single-layer interconnections. A delay time analysis reveals that this speed increase is due to the decrease in interconnection propagation delay.

An active integrated antenna (AIA) oscillator consisting of an active circuit and planar antenna on the same substrate can be used as a high-performance, low-cost, small component for millimeter-to-sub-millimeter wave applications. We describe a highly extended, finite-difference-time-domain full-wave analysis method for designing AIA circuits precisely. It treats active devices as distributed elements. Using this method and 0.1-µm-gate InP-based HEMTs, we fabricated W-band AIA oscillators with an oscillation frequency of 111 GHz.

Noise characteristics of InAlAs/InGaAs HEMT's passivated by SiN are investigated to ascertain their suitability for practical applications in circuit such as MMIC's. A 0.18-µm-gate-length device with 125-µm-gate width and 8-gate fingers showed the lowest minimum noise figure of 0.43 dB at 26 GHz with an associated gain of 8.5 dB of any passivated device ever reported. This value is also comparable to the lowest reported minimum noise figure obtained by bare InAlAs/InGaAs HEMT's in spite of increased parasitic capacitances due to the SiN passivation. Thes excellent noise performance was achieved by employing non-alloyed ohmic contact, a T-shaped gate geometry and a multi-finger gate pattern. To reduce the contact resistance of the non-alloyed ohmic contact, a novel n+-InGaAs/n+-InAlAs cap layer was used resulting in a very low contact resistance of 0.09 Ωmm and a low sheet resistance for all layers of 145 Ω/sq. No increase in these resistances was observed after SiN passivation, and a very low source resistance of 0.16 Ωmm was obtained. An analysis of equivalent circuit parameters revealed that the T-shaped gate and multi-finger gate pattern drastically decrease gate resistance.

A novel fabrication technology for lateral scale-down of sub-100-nm-gate InP-based HEMTs is presented. The fabricated device, whose structure features a reduced distance between the gate and ohmic metals of less than 100 nm, exhibits low ohmic resistances and improved DC and RF characteristics with good uniformity across a wafer. A fabricated 130-nm-gate lattice-matched InAlAs/InGaAs HEMT exhibits an extrinsic transconductance of 1.3 S/mm. This is 25% increase compared to that of a HEMT fabricated with our conventional process, which is explained by the reduction of RS. The average current-gain-cutoff-frequency (fT) of 261 GHz was obtained with a small deviation of 9.0 GHz. Uniform characteristics with high yield were also confirmed for HEMTs with shorter gates. The average fT of 290 GHz with a standard deviation of 9.3 GHz was obtained for 55-nm-gate HEMTs. The developed fabrication technology is promising for improving the electrical characteristics of sub-100-nm-gate InP-based HEMTs and for their integration.

We discuss delay times derived from the current gain cutoff frequency of a heterostructure field effect transistor and describe three types of novel channel structures for millimeter-wave InP-based HFETs. The first structure discussed is a lattice-matched InGaAs HEMT with high state-of-the art performance. The second structure is an InAs-inserted InGaAs HEMT which harnesses the superior transport properties of InAs. Fabricated devices show high electron mobility of 12,800 cm2/Vs and high transconductance over 1.4 S/mm for a 0.6-µm-gate length. The effective saturation velocity in the device derived from the current gain cutoff frequency in 3.0107 cm/s. The third one is an InGaAs/InP double-channel HFET that utilizes the superior transport properties of InP at a high electric field. Fabricated double-channel devices show kink-free characteristics, high carrier density of 4.51012 cm-2 and high transconductance of 1.3 S/mm for a 0.6-µm-gate length. The estimated effective saturation velocity in these devices is 4.2107 cm/s. Also included is a discussion of the current gain cutoff frequency of ultra-short channel devices.

A 20 GHz band monolithic low noise amplifier combining improved SAINT-FET technology and optimized circuit design has been developed. The amplifier has a measured noise figure of less than 3.5 dB with a minimum gain of 4.2 dB over the 18.5 GHz to 20 GHz range. The optimal noise figure is 2.9 dB with a gain of 5.5 dB at 19 GHz. Standard threshold-voltage deviation of the process monitor FRTs is only 70 mV over the entire area of the 2-inch wafer.