IEICE TRANSACTIONS on Electronics
Novel Fabrication Technology for High Yield Sub-100-nm-Gate InP-Based HEMTs
Summary :
A novel fabrication technology for lateral scale-down of sub-100-nm-gate InP-based HEMTs is presented. The fabricated device, whose structure features a reduced distance between the gate and ohmic metals of less than 100 nm, exhibits low ohmic resistances and improved DC and RF characteristics with good uniformity across a wafer. A fabricated 130-nm-gate lattice-matched InAlAs/InGaAs HEMT exhibits an extrinsic transconductance of 1.3 S/mm. This is 25% increase compared to that of a HEMT fabricated with our conventional process, which is explained by the reduction of RS. The average current-gain-cutoff-frequency (fT) of 261 GHz was obtained with a small deviation of 9.0 GHz. Uniform characteristics with high yield were also confirmed for HEMTs with shorter gates. The average fT of 290 GHz with a standard deviation of 9.3 GHz was obtained for 55-nm-gate HEMTs. The developed fabrication technology is promising for improving the electrical characteristics of sub-100-nm-gate InP-based HEMTs and for their integration.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.7 pp.949-953
- Publication Date
- 2006/07/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.7.949
- Type of Manuscript
- Special Section PAPER (Special Section on Heterostructure Microelectronics with TWHM2005)
- Category
- Millimeter-Wave Devices
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Hideaki MATSUZAKI, Takashi MARUYAMA, Takatomo ENOKI, Masami TOKUMITSU, "Novel Fabrication Technology for High Yield Sub-100-nm-Gate InP-Based HEMTs" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 7, pp. 949-953, July 2006, doi: 10.1093/ietele/e89-c.7.949.
Abstract: A novel fabrication technology for lateral scale-down of sub-100-nm-gate InP-based HEMTs is presented. The fabricated device, whose structure features a reduced distance between the gate and ohmic metals of less than 100 nm, exhibits low ohmic resistances and improved DC and RF characteristics with good uniformity across a wafer. A fabricated 130-nm-gate lattice-matched InAlAs/InGaAs HEMT exhibits an extrinsic transconductance of 1.3 S/mm. This is 25% increase compared to that of a HEMT fabricated with our conventional process, which is explained by the reduction of RS. The average current-gain-cutoff-frequency (fT) of 261 GHz was obtained with a small deviation of 9.0 GHz. Uniform characteristics with high yield were also confirmed for HEMTs with shorter gates. The average fT of 290 GHz with a standard deviation of 9.3 GHz was obtained for 55-nm-gate HEMTs. The developed fabrication technology is promising for improving the electrical characteristics of sub-100-nm-gate InP-based HEMTs and for their integration.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.7.949/_p
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@ARTICLE{e89-c_7_949,
author={Hideaki MATSUZAKI, Takashi MARUYAMA, Takatomo ENOKI, Masami TOKUMITSU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Novel Fabrication Technology for High Yield Sub-100-nm-Gate InP-Based HEMTs},
year={2006},
volume={E89-C},
number={7},
pages={949-953},
abstract={A novel fabrication technology for lateral scale-down of sub-100-nm-gate InP-based HEMTs is presented. The fabricated device, whose structure features a reduced distance between the gate and ohmic metals of less than 100 nm, exhibits low ohmic resistances and improved DC and RF characteristics with good uniformity across a wafer. A fabricated 130-nm-gate lattice-matched InAlAs/InGaAs HEMT exhibits an extrinsic transconductance of 1.3 S/mm. This is 25% increase compared to that of a HEMT fabricated with our conventional process, which is explained by the reduction of RS. The average current-gain-cutoff-frequency (fT) of 261 GHz was obtained with a small deviation of 9.0 GHz. Uniform characteristics with high yield were also confirmed for HEMTs with shorter gates. The average fT of 290 GHz with a standard deviation of 9.3 GHz was obtained for 55-nm-gate HEMTs. The developed fabrication technology is promising for improving the electrical characteristics of sub-100-nm-gate InP-based HEMTs and for their integration.},
keywords={},
doi={10.1093/ietele/e89-c.7.949},
ISSN={1745-1353},
month={July},}
Copy
TY - JOUR
TI - Novel Fabrication Technology for High Yield Sub-100-nm-Gate InP-Based HEMTs
T2 - IEICE TRANSACTIONS on Electronics
SP - 949
EP - 953
AU - Hideaki MATSUZAKI
AU - Takashi MARUYAMA
AU - Takatomo ENOKI
AU - Masami TOKUMITSU
PY - 2006
DO - 10.1093/ietele/e89-c.7.949
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2006
AB - A novel fabrication technology for lateral scale-down of sub-100-nm-gate InP-based HEMTs is presented. The fabricated device, whose structure features a reduced distance between the gate and ohmic metals of less than 100 nm, exhibits low ohmic resistances and improved DC and RF characteristics with good uniformity across a wafer. A fabricated 130-nm-gate lattice-matched InAlAs/InGaAs HEMT exhibits an extrinsic transconductance of 1.3 S/mm. This is 25% increase compared to that of a HEMT fabricated with our conventional process, which is explained by the reduction of RS. The average current-gain-cutoff-frequency (fT) of 261 GHz was obtained with a small deviation of 9.0 GHz. Uniform characteristics with high yield were also confirmed for HEMTs with shorter gates. The average fT of 290 GHz with a standard deviation of 9.3 GHz was obtained for 55-nm-gate HEMTs. The developed fabrication technology is promising for improving the electrical characteristics of sub-100-nm-gate InP-based HEMTs and for their integration.
ER -
English
