We have developed a planar devic technology consisting of 0.15-µm Au/WSiN-gate GaAs-heterostructure MESFETs (HMESFETs) fabricated by self-aligned ion-implantation. The gate-drain breakdown voltage has been improved to 10 V by using an asymmetric LDD structure, and the maximum oscillation frequency is 190 GHz. Because asymmetric and symmetric FETs can be fabricated simultaneously, this technology is suitable for use in making multi-functional millimeter-wave MMICs.

A divide-four static frequency divider is fabricated to evaluate the ultra-high-speed performance of Au/WSiN gate GaAs MESFETs. The divider consists of two T-type flip-flops (T-F/F) ans three buffers based on low-power source-coupled FET logic (LSCFL). The divider operates up to 31.4 GHz at room temperature at power dissipation of 150 mW per T-F/F using Au/WSiN gate GaAs MESFETs well scaled down to 0.3 µm gate-length.

The authors report on a 22-Gbit/s static decision IC fabricated with 0. 12-µm GaAs MESFETs. The key to attaining high-speed decision IC is the employment of a novel high-speed D-type flip-flop (D-FF). The D-FF succeeds in faster operation through the simplification of the circuitry and the reduction of the transition time of the output voltages.

A 0.1-µm gate-length GaAs MESFET technology is reported. A 48.3-GHz dynamic-frequency divider, and an amplifier with 20-dB gain and 17.5-GHz bandwidth are successfully fabricated by integrating over-100-GHz-cut-off frequency MESFETs using a new lightly-doped drain structure with a buried p-layer (BP-LDD) device structure.

A procedure for quickly developing highly integrated multifunctional MMICs by using the three-dimensional masterslice MMIC technology has been developed. The structures and advanced features of this technology, such as miniature transmission lines, a broadside coupler, and miniature function block circuits, enable multifunctional MMICs to be quickly and easily developed. These unique features and basic concept of the masterslice technology are discussed and reviewed to examine the advantages of this technology. As an example of quick MMIC development, an amplifier, a mixer, and a down-converter are fabricated on a newly designed master array.

A novel fabrication technology for lateral scale-down of sub-100-nm-gate InP-based HEMTs is presented. The fabricated device, whose structure features a reduced distance between the gate and ohmic metals of less than 100 nm, exhibits low ohmic resistances and improved DC and RF characteristics with good uniformity across a wafer. A fabricated 130-nm-gate lattice-matched InAlAs/InGaAs HEMT exhibits an extrinsic transconductance of 1.3 S/mm. This is 25% increase compared to that of a HEMT fabricated with our conventional process, which is explained by the reduction of RS. The average current-gain-cutoff-frequency (fT) of 261 GHz was obtained with a small deviation of 9.0 GHz. Uniform characteristics with high yield were also confirmed for HEMTs with shorter gates. The average fT of 290 GHz with a standard deviation of 9.3 GHz was obtained for 55-nm-gate HEMTs. The developed fabrication technology is promising for improving the electrical characteristics of sub-100-nm-gate InP-based HEMTs and for their integration.

BP-LDD n+ self-aligned GaAs-MESFETs with Au/WSiN bilayer gate have been fabricated on 3-indiameter GaAs substrate which demonstrates the splendid potentiality of GaAs-MESFET technology. The 0.3-µm gate GaAs-MESFETs show a peak extrinsic transconductance of 550 mS/mm with a threshold voltage of -1.4 V. From S-parameter measurement, the MESFETs demonstrate a peak cutoff frequency of 56 GHz and a maximum oscillation frequency of 120 GHz. Moreover, a monolithic distributed amplifier has been fabricated using the four GaAs-MESFETs with 0.3 µm gate length. The amplifier has achieved a high gain of 7.3 dB with a 3-dB down frequency bandwidth of 0.5-30 GHz.

Novel three-dimensional structures for passive elements--inductors, capacitors, transmission lines, and airbridges--have been developed to reduce the area they consume in GaAs MMICs. These structures can be formed with a simple technology by electroplating along the sidewalls of a photoresist. Adopting the new structures, most passive elements in MMICs have been shrunk to less than 1/4 the size of conventional ones.

As a review of the InP HEMT technology and its applications to logic ICs, the two-step-recess gate structure, which is now widely used in high-performance InP HEMTs, and its application to optoelectronic ICs are described. This paper also covers the topic of the gate delay analysis that reveals that the parasitic delay becomes the primary cause of the gate delay in sub-100-nm gate regime. For future challenge for logic applications, ways to reduce the off-state transistor current is also discussed.

A design scheme for a high-speed differential-input limiting transimpedance amplifier (TIA) was developed. The output-stage amplifier of the TIA is investigated in detail in order to suppress undershoot and ringing in the output waveform. The amplifier also includes a peak detector for the received signal strength indicator (RSSI) output, which is used to control the optical demodulator for differential-phase-shift-keying or differential-quadrature-phase-shift-keying formats. The limiting TIA was fabricated on the basis of 1-µm emitter-width InP-based heterojunction-bipolar-transistor (HBT) IC technology. Its differential gain is 39 dB, its 3-dB bandwidth is 27 GHz, and its estimated differential transimpedance gain is 73 dBΩ. The obtained output waveform shows that the developed design scheme is effective for suppressing undershoot and ringing.

The authors report on a 40-Gbit/s superdynamic decision IC fabricated with 0.12-µm GaAs MESFETs. The key to attaining high-speed decision IC is not only high-speed flip-flop circuits but also wideband input and output buffer circuits. 40 Gbit/s is the fastest operating speed of decision ICs fabricated with GaAs MESFETs.

A 3-bit flash analog-to-digital converter (ADC) for electronic dispersion compensation (EDC) was developed using InP HBTs. Nyquist operation was confirmed up to 24 Gsps, which enables oversampling acquisition for 10 Gbit/s non-return-to-zero (NRZ) signals. The ADC can also be operated at up to 37 Gsps for low input frequencies. To reduce aperture jitter and achieve a wide band of over 7 GHz, an analog input signal for all pre-amplifiers and a clock signal for all latched comparators are provided as traveling waves through coplanar transmission lines. EDC was demonstrated by capturing a 10-Gbit/s pseudo-random bit stream (PRBS) with the waveform degraded by polarization-mode dispersion (PMD). By using the captured data, we confirmed that a calculation of a transversal filter mitigates PMD.