Implementation of RFID reader/writer on software defined radio is studied in this paper. The target RFID is ISO18000-3 mode 2 which has 8 reply channels for simultaneous communication with 8 different RFID tags. In the software defined radio architecture, the 8 reply channels are sampled at a single A/D converter and separated by digital down converters, whereas conventional RFID architecture has redundant 8 parallel analog down converters. A novel multi-stage transmultiplexing digital down converter is proposed for efficient implementation of multi-channel digital down converter. Moreover the proposed architecture is implemented on a FPGA evaluation board, and validity of the system is confirmed on a real hardware. The proposed architecture can be applied to multi-channel receiver for dynamic spectrum system in the cognitive radio.

This paper proposes a set of three IF-band MMICs for high-speed wireless communication systems. The first of the circuits in this chip set is an MMIC logarithmic limiting receiver amplifier. This amplifier utilizes the self-phase distortion compensation technique, combining a common-source FET and a common-drain FET, to reduce phase distortion. The limiting characteristics were gain of more than 65 dB, 2. 2-dBm saturated output power and phase deviation of less than 5. A logarithmic accuracy of 2 dB and RSSI change coefficient of more than 11 mV/dB were also achieved. Typical power consumption was less than 0. 58 W with the supply voltages of +3 V and -2 V. The second of the fabricated circuits is an MMIC transmitter amplifier with more than 24-dB gain at 140 MHz. And the third of the fabricated circuits is an MMIC 90 signal divider and combiner. This MMIC combines a set of amplifiers with a set of dividers having a constant phase difference of 90. Thus the isolation between the transmission port and the reception port is obtained. The chip size is less than 1/100 that of a commercial 140-MHz-band 90 coupler. At the frequency of 140 MHz, the mean transmission loss is about 2. 1 dB for the divider part and 3. 0 dB for the combiner part. Furthermore, in the frequency range of 130 MHz to 150 MHz, signal leakage from the transmission port to the reception port is suppressed by more than 24 dB.

This paper proposes a novel broad-band MMIC VCO using an active inductor. This VCO is composed of a serial resonant circuit, in which the capacitor is in series with an active inductor that has a constant negative resistance. Since the inductance value of this active inductor is inversely proportional to the square of the transconductance and can vary widely with the FETs gate bias control, a broad-band oscillation tuning range can be obtained. Furthermore, since this active inductor can generate a constant negative resistance of more than 50Ω, the proposed VCO can oscillate against a 50Ω output load immediately without using additional impedance transformers. We have fabricated the VCO using a GaAs MESFET process. A frequency tuning range of more than 50%, from 1.56 to 2.85 GHz, with an output power of 4.41.0 dBm, was obtained. With a carrier of 2. 07 GHz, the phase noise at 1-MHz offset was less than -110 dBc/Hz. The chip size was less than 0. 61 mm2, and the power consumption was 80 mW. This broad-band analog design can be used at microwave frequencies in PLL applications as a compact alternative to other types of oscillator circuits.

Recently fiber optic links have been applied to radio signal distribution networks and also to signal feeder networks for phased array antennas, because they are able to offer wide bandwidth for achieving the high bit-rates and large capacity needed in the multimedia age. In these networks, a great many modules are needed to convert optical signals to radio signals. In order to reduce the complexity and cost of these modules, direct optical control techniques, which inject optical signals directly into microwave circuits, are very attractive. Thus, this paper proposes a novel optical control technique using tunable inductance circuits. This technique employs direct illumination as a means of optically tuning the inductance. Since the inductance value is inversely proportional to the square of the transconductance, it varies widely when the FET is directly illuminated. With direct illumination, the measured inductance variation in an experimental inductance circuit built with Pseudomorphic AlGaAs/InGaAs/GaAs HEMTs is more than 20 % from 0.5 to 2 GHz. As an application, a direct optically controlled oscillator was fabricated. The measured optical tuning range of the oscillation frequency is more than 19 % with an output power of -51 dBm. This is a promising technique for a variety of devices, including optically controlled oscillators, filters, phase shifters, and active antennas.

This paper presents a novel distortion compensation technique using an active inductor. First, we describe the input-reflection-coefficient characteristics of a GaAs MESFET active inductor when input power increases. We show that the inductor exhibits positive amplitude deviation and negative/positive phase deviation as the input power increases when the biases of the FETs are set appropriately. The chip size of the fabricated active inductor is less than 0.52 mm2. Then, we show that third-order intermodulation is improved when the active inductor is used as a predistortion linearizer. Third-order intermodulation was improved over the output range from 14 dBm to 25 dBm, and at the output of 15 dBm, third-order intermodulation was improved approximately by 9 dB when the predistortion linearizer was introduced. The active inductor can thus function as a miniaturized predistortion linearizer by using it in the input matching circuit of a power amplifier. This technique can be applied in the miniaturization of wireless communication devices.

This paper describes a novel quasi-transmission-line variable-reactance circuit that extends the variable-phase range of phase shifters. It consists of a transmission line and two shunt varactors. By appropriately choosing the characteristic impedance and electrical length of the transmission line, the variable-phase range can be significantly increased. Since the proposed circuit can be fabricated by the conventional MESFET process, a phase shifter can be integrated with other functional circuits. This enables fully monolithic integration of RF circuits as a one-chip multi-functional MMIC in radio communication systems. The variable-phase range of the prototype X-band monolithic phase shifter is 208 degrees, which is approximately four times as large as that of conventional one.

This paper proposes a low distortion technique which reduces transmitter intermodulation. It is shown that one of the third order transmitter intermodulation products generated can be reduced by using a parallel amplifier configuration which includes a 45 divider and a 45 combiner. It is already known that the other third order transmitter intermodulation product can be reduced by using a parallel amplifier configuration using 90 hybrids. Thus, all of the third order transmitter intermodulation can be reduced by combining these configurations. This paper also shows the experimental results obtained with a parallel amplifier using 90 hybrids and one using a 45 divider and combiner in the K-band. The spectra of these amplifiers are compared, and it is found that third order transmitter intermodulation can be reduced by more than 29 dB in the parallel amplifier using the 45 divider and combiner.

An MMIC variable-gain amplifier, which improves the transmission phase deviation caused by gain control, is presented. At first, it is shown that by controlling both the common-gate FET's gate bias voltage and the common-source FET's gate bias voltage, the transmission phase deviation caused by gain control of the variable-gain amplifier using a cascode-connected FET is greatly improved. In this case it is not desirable to control both of the gate bias voltages independently, because of the complexity. Thus we propose two simple gate bias voltage control circuits controlling both of the gate bias voltages, in which only one of the two gate bias voltages is controlled independently and the other is controlled dependently. Then we apply these circuits to the 1. 9-GHz-band variable-gain amplifier using the cascode-connected FET. One of the control circuits is the gate bias voltage control circuit using two resistors. It is confirmed that, by applying the newly proposed circuit, phase deviation is suppressed, from between 0and 30to between 3and 5, with 25-dB gain control. The other circuit is the gate bias voltage control circuit using the FET's nonlinear characteristics. It is confirmed that, by applying the newly proposed circuit, phase deviation is suppressed, from between 0and 44to between 6and 3 with 30-dB gain control. This is a promising technique for reducing the transmission phase deviation caused by gain control of the amplifiers used in active phased array antennas.

This paper demonstrates a polyimide/alumina-ceramic multilayer MIC analog phase shifter with a large phase shift. First, a novel active inductor, similar to the previously reported active inductor but with a shunt variable resistor inserted in the feedback loop, is proposed for miniaturizing the circuit. The chip size of the fabricated GaAs MESFET active inductor is less than 0. 52 mm2. Next, a low-loss analog phase shifter with a large phase shift is presented. This is constructed in an MIC structure with the active inductors, the varactor diodes and the low-loss polyimide/alumina-ceramic multilayer broad-side coupler. Furthermore, since the amount of the phase shift is the sum of the two individual tuning ranges attributed to the active inductors and varactor diodes, a large phase shift is obtained compared to the case where only the varactor diodes are tunable. Thus, a phase shift of more than 270 within 2-dB insertion loss from 2. 1 to 2. 4 GHz is obtained with the fabricated single-stage reflection-type analog phase shifter. The total power consumption is less than 80 mW.

A new impedance matched film carrier is developed to package uniplanar MMICs. The carrier has an insulating polyimide film on which RF, DC bias, and ground conductive areas are formed. The areas extend into bonding windows, which are etched in the polyimide film, and the extended portions form inner and outer leads. The interconnection of the inner and outer leads to MMIC-electrode pads is highly reliable because of the gold-plated bumps formed at the distal ends of the inner and outer leads. This carrier has an insertion loss of less than 0.2 dB/mm without resonance over the frequency range from DC to 30 GHz. The electrical performance of the GaAs MMIC module with this carrier is almost equal to that of the MMIC measured directly on-wafer.

We propose linearization techniques for MMIC amplifiers. The key points of these techniques are increased linearity of a newly-developed low-distortion MESFET (LD-FET) and maximized IP3 by combining the LD-FET with a high-gain depletion-mode MESFET (D-FET) with no increase in power consumption. The LD-FET is characterized by its unique channel dopant-profile prepared by a buried p-type ion-implantation and double n-type ion-implantations with high- and low-acceleration energies. This FET achieves flatter behavior in terms of mutual conductance (gm) compared with conventional MESFETs irrespective of changes in the gate bias voltage (Vgs). A self-alignment/selective ion-implantation process enables the LD-FET and D-FET to be fabricated simultaneously. This process encourages IP3 maximization of the multi-stage amplifier by appropriately combining the advantages of the two differently characterized MESFETs. We fabricated and tested a highly linearized two-stage MMIC amplifier utilizing the proposed techniques, and found that its third-order intermodulation ratio (IMR) performance was 8.7 dB better than that of conventional MMIC amplifiers at an input signal level of -20 dBm with no increase in current dissipation. The configuration constructed by using the proposed techniques equivalently reduces the current dissipation of the second stage to 1/2.72 times that of the conventional configuration, which requires a 2.72 times larger D-FET at the second stage to obtain an 8.7-dB IMR improvement. Furthermore, we were able to improve the IMR by 3.5 dB by optimizing the gate bias conditions for the LD-FET. These results confirm the validity of the proposed techniques.

We propose a new phase interpolator that provides precise fractional phase pulses without the need to adjust circuit constants. The variable phases are produced by detecting the coincidence of two voltages, the ramp wave and the threshold voltage. The new phase interpolator can keep the same ramp wave slope and the same threshold voltage for different output phases. This significantly reduces the power dissipation of the voltage comparator. This phase interpolator can be applied to various timing circuits and clock generators, such as frequency multipliers and direct digital synthesizers. We present a novel frequency doubler, a novel frequency tripler, a direct digital synthesizer (DDS), and a novel wideband DDS (WDDS) as applications of our new phase interpolator, which uses 0.35-mm CMOS process technology. Experimental results confirm the functionarity of the new phase interpolator. An 8-bit complete DDS IC dissipates only 2.1 mA at a 50-MHz clock rate and a supply voltage of 2.8 V.

A Ku-band monolithic voltage controlled oscillator (VCO) has been developed. All the circuit elements for the VCO, i.e., an FET, a control diode, an output matching circuit, a stabilizer, and associated circuitary were integrated on a single chip. This VCO is characterized by using a unique stabilizer. The VCO with its stabilizer has shown stable oscillations across a tuning bandwidth covering 12.30 to 12.80 GHz with control voltage of 1 to 3.5 V. The output terminal of the chip can be directly connected to 50 ohm loads and requires no additional attenuator or isolator to stabilize it.

A 20 GHz band monolithic low noise amplifier combining improved SAINT-FET technology and optimized circuit design has been developed. The amplifier has a measured noise figure of less than 3.5 dB with a minimum gain of 4.2 dB over the 18.5 GHz to 20 GHz range. The optimal noise figure is 2.9 dB with a gain of 5.5 dB at 19 GHz. Standard threshold-voltage deviation of the process monitor FRTs is only 70 mV over the entire area of the 2-inch wafer.

A 2.7-V Si-bipolar quadrature modulator with a 90 phase shifter consisting of a frequency doubler and a master-slave flip-flop is described. The modulator operates over a wide bandwidth (0.95 to 1.88 GHz) without any tuning or adjustments. It is implemented using 20-GHz Si-bipolar technology and dissipates 97 mW at 2.7 V. An image ratio of less than -40 dBc is obtained between 1.1 and 1.8 GHz. Moreover, third-order harmonic products are less than -40 dBc and carrier leakage is less than -30 dBc.

A 3-bit flash analog-to-digital converter (ADC) for electronic dispersion compensation (EDC) was developed using InP HBTs. Nyquist operation was confirmed up to 24 Gsps, which enables oversampling acquisition for 10 Gbit/s non-return-to-zero (NRZ) signals. The ADC can also be operated at up to 37 Gsps for low input frequencies. To reduce aperture jitter and achieve a wide band of over 7 GHz, an analog input signal for all pre-amplifiers and a clock signal for all latched comparators are provided as traveling waves through coplanar transmission lines. EDC was demonstrated by capturing a 10-Gbit/s pseudo-random bit stream (PRBS) with the waveform degraded by polarization-mode dispersion (PMD). By using the captured data, we confirmed that a calculation of a transversal filter mitigates PMD.

A single-stage dual-frequency matching network that can simultaneously transform a transistor reflection coefficient to zero at two separate frequencies (a lower frequency fL and a higher frequency fH) is proposed. The network is made by adding a shorted stub, the length of which is a quarter-wavelength at fH, to a conventional L-section matching network composed of a series transmission line and an open stub. The concept of dual-frequency matching is based on the fact that the synthesized shunt admittance of the open and shorted stubs changes from capacitive at fH to inductive at fL. By means of the single-stage matching network, broad-band amplifier performance, the bandwidth of which is given as (fH-fL), can be easily obtained with almost the same design procedures and circuit area used for conventional narrow-band amplifiers. In this paper, the function of the dual-frequency matching network is analyzed in detail and an application of the matching technique to a two-stage amplifier is described. A broad-band performance of |S21|>7.4 dB at 27.0-62.5 GHz has been achieved with a GaAs P-HEMT two-stage MMIC amplifier.

A power amplifier employing a novel linearizing technique is proposed and is applied to digital mobile communication systems. The amplifier offers both high efficiency and excellent adjacent-channel power leakage (ACP) characteristics. The power added efficiency (PAE) of the proposed amplifier is 51% with an ACP of 45 dBc, which is the PDC standard (one of the Japanese mobile communication systems standards). This amplifier can be applied to various systems merely by changing the ROM data.