This paper proposes a set of three IF-band MMICs for high-speed wireless communication systems. The first of the circuits in this chip set is an MMIC logarithmic limiting receiver amplifier. This amplifier utilizes the self-phase distortion compensation technique, combining a common-source FET and a common-drain FET, to reduce phase distortion. The limiting characteristics were gain of more than 65 dB, 2. 2-dBm saturated output power and phase deviation of less than 5
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Hitoshi HAYASHI, Masahiro MURAGUCHI, "An IF-Band MMIC Chip Set for High-Speed Wireless Communication Systems" in IEICE TRANSACTIONS on Electronics,
vol. E81-C, no. 1, pp. 63-69, January 1998, doi: .
Abstract: This paper proposes a set of three IF-band MMICs for high-speed wireless communication systems. The first of the circuits in this chip set is an MMIC logarithmic limiting receiver amplifier. This amplifier utilizes the self-phase distortion compensation technique, combining a common-source FET and a common-drain FET, to reduce phase distortion. The limiting characteristics were gain of more than 65 dB, 2. 2-dBm saturated output power and phase deviation of less than 5
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e81-c_1_63/_p
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@ARTICLE{e81-c_1_63,
author={Hitoshi HAYASHI, Masahiro MURAGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={An IF-Band MMIC Chip Set for High-Speed Wireless Communication Systems},
year={1998},
volume={E81-C},
number={1},
pages={63-69},
abstract={This paper proposes a set of three IF-band MMICs for high-speed wireless communication systems. The first of the circuits in this chip set is an MMIC logarithmic limiting receiver amplifier. This amplifier utilizes the self-phase distortion compensation technique, combining a common-source FET and a common-drain FET, to reduce phase distortion. The limiting characteristics were gain of more than 65 dB, 2. 2-dBm saturated output power and phase deviation of less than 5
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - An IF-Band MMIC Chip Set for High-Speed Wireless Communication Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 63
EP - 69
AU - Hitoshi HAYASHI
AU - Masahiro MURAGUCHI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 1998
AB - This paper proposes a set of three IF-band MMICs for high-speed wireless communication systems. The first of the circuits in this chip set is an MMIC logarithmic limiting receiver amplifier. This amplifier utilizes the self-phase distortion compensation technique, combining a common-source FET and a common-drain FET, to reduce phase distortion. The limiting characteristics were gain of more than 65 dB, 2. 2-dBm saturated output power and phase deviation of less than 5
ER -