A clock recovery circuit is a key component in optical communication systems. In this paper, an optoelectronic clock recovery circuit is reported that monolithically integrates a resonant tunneling diode (RTD) and a uni-traveling-carrier photodiode (UTC-PD). The circuit is an injection-locked-type RTD oscillator that uses the photo-current generated by the UTC-PD. Fundamental and sub-harmonic clock extraction is confirmed for the first time with good clock recovery circuit characteristics. The IC extracts an electrical 11.55-GHz clock signal from 11.55-Gbit/s RZ optical data streams with the wide locking range of 450 MHz and low power dissipation of 1.3 mW. Furthermore, the extraction of a sub-harmonic clock from 23.1-Gbit/s and 46.2-Gbit/s input data streams is also confirmed in the wider locking range of 600 MHz. The RMS jitter as determined from a single sideband phase noise measurement is extremely low at less than 200 fs in both cases of clock and sub-harmonic clock extraction. To our knowledge, the product of the output power and operating frequency of the circuit is the highest ever reported for injection-locked-type RTD oscillators. These characteristics indicate the feasibility of the optoelectronic clock recovery circuit for use in future ultra-high-speed fully monolithic receivers.

A 50-Gbit/s demultiplexer IC module that uses 0.1-µm InAlAs/InGaAs/InP HEMTs is reported. The maximum error-free operation bit-rate of a fabricated module is 50 Gbit/s, and a wide phase margin of 170 degrees is obtained at 43 Gbit/s. 50-Gbit/s demultiplexing is the fastest performance of all packaged demultiplexer ICs yet reported.

This paper proposes an efficient reference image sharing method for the image-division parallel video encoding architecture. This method efficiently reduces the amount of data transfer by using pre-transfer with area prediction and on-demand transfer with a transfer management table. Experimental results show that the data transfer can be reduced to 19.8-35.3% of the conventional method on average without major degradation of coding performance. This makes it possible to reduce the required bandwidth of the inter-chip transfer interface by saving the amount of data transfer.

A design scheme for a high-speed differential-input limiting transimpedance amplifier (TIA) was developed. The output-stage amplifier of the TIA is investigated in detail in order to suppress undershoot and ringing in the output waveform. The amplifier also includes a peak detector for the received signal strength indicator (RSSI) output, which is used to control the optical demodulator for differential-phase-shift-keying or differential-quadrature-phase-shift-keying formats. The limiting TIA was fabricated on the basis of 1-µm emitter-width InP-based heterojunction-bipolar-transistor (HBT) IC technology. Its differential gain is 39 dB, its 3-dB bandwidth is 27 GHz, and its estimated differential transimpedance gain is 73 dBΩ. The obtained output waveform shows that the developed design scheme is effective for suppressing undershoot and ringing.

A 3-bit flash analog-to-digital converter (ADC) for electronic dispersion compensation (EDC) was developed using InP HBTs. Nyquist operation was confirmed up to 24 Gsps, which enables oversampling acquisition for 10 Gbit/s non-return-to-zero (NRZ) signals. The ADC can also be operated at up to 37 Gsps for low input frequencies. To reduce aperture jitter and achieve a wide band of over 7 GHz, an analog input signal for all pre-amplifiers and a clock signal for all latched comparators are provided as traveling waves through coplanar transmission lines. EDC was demonstrated by capturing a 10-Gbit/s pseudo-random bit stream (PRBS) with the waveform degraded by polarization-mode dispersion (PMD). By using the captured data, we confirmed that a calculation of a transversal filter mitigates PMD.

This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/-0.07 LSB and +0.27/-0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24 GS/s are also obtained. The total power consumption is as low as 0.88 W with a supply voltage of -4.0 V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5 bits or more.

A clock recovery circuit is a key component in optical communication systems. In this paper, an optoelectronic clock recovery circuit is reported that monolithically integrates a resonant tunneling diode (RTD) and a uni-traveling-carrier photodiode (UTC-PD). The circuit is an injection-locked-type RTD oscillator that uses the photo-current generated by the UTC-PD. Fundamental and sub-harmonic clock extraction is confirmed for the first time with good clock recovery circuit characteristics. The IC extracts an electrical 11.55-GHz clock signal from 11.55-Gbit/s RZ optical data streams with the wide locking range of 450 MHz and low power dissipation of 1.3 mW. Furthermore, the extraction of a sub-harmonic clock from 23.1-Gbit/s and 46.2-Gbit/s input data streams is also confirmed in the wider locking range of 600 MHz. The RMS jitter as determined from a single sideband phase noise measurement is extremely low at less than 200 fs in both cases of clock and sub-harmonic clock extraction. To our knowledge, the product of the output power and operating frequency of the circuit is the highest ever reported for injection-locked-type RTD oscillators. These characteristics indicate the feasibility of the optoelectronic clock recovery circuit for use in future ultra-high-speed fully monolithic receivers.

This paper is a report on a high ESD breakdown-voltage InP HBT transimpedance amplifier IC for optical video distribution systems. To make ESD breakdown-voltage higher, we designed ESD protection circuits integrated in the TIA IC using base-collector/base-emitter diodes of InP HBTs and resistors. These components for ESD protection circuits have already existed in the employed InP HBT IC process, so no process modifications were needed. Furthermore, to meet requirements for use in optical video distribution systems, we studied circuit design techniques to obtain a good input-output linearity and a low-noise characteristic. Fabricated InP HBT TIA IC exhibited high human-body-model ESD breakdown voltages (±1000 V for power supply terminals, ±200 V for high-speed input/output terminals), good input-output linearity (less than 2.9-% duty-cycle-distortion), and low noise characteristic (10.7 pA/ averaged input-referred noise current density) with a -3-dB-down higher frequency of 6.9 GHz. To the best of our knowledge, this paper is the first literature describing InP ICs with high ESD-breakdown voltages.

An ultra-fast optoelectronic decision circuit using resonant tunneling diodes (RTD's) and a uni-traveling-carrier photodiode (UTC-PD) is proposed. The circuit employs two cascaded RTD's for ultra-fast logic operation and one UTC-PD that offers a direct optical input interface. This novel configuration is suitable for ultra-fast decision operation. Two types of decision circuits are introduced: a positive-logic type and a negative-logic type. Operations of these circuits were simulated using SPICE with precisely investigated RTD and UTC-PD models. In terms of circuit speed, 40-Gbit/s decision and 80-Gbit/s demultiplexing were expected. Furthermore, the superiority of the negative-logic type in terms of the circuit operating margin and the relationship between input peak photocurrent and effective logic swing were clarified by SPICE simulations. In order to confirm the basic functions of the circuits and the accuracy of the simulations, circuits were fabricated by monolithically integrating InP-based RTD's and UTC-PD's. The circuits successfully exhibited 40-Gbit/s decision operation and 80-Gbit/s demultiplexing operation with less than 10-mW power dissipation. The superiority of the negative-logic type circuit for the circuit operation was confirmed, and the relationship between the input peak photocurrent and the effective logic swing was as predicted.

We experimentally studied the polarization mode dispersion (PMD) tolerance of an feed-forward equalizer (FFE) electronic dispersion compensation (EDC) IC in the absence of adaptive control, in 43-Gbit/s RZ-DQPSK transmission. Using a 3-tap FFE IC composed of InP HBTs, differential group delay (DGD) tolerance at a 2-dB Q penalty is shown to be extended from 25 ps to up to 29 ps. When a polarization scrambler is used, the tolerance is further extended to 31 ps. This value is close to the tolerance obtained with adaptive control, without a polarization scrambler.

An SCFL-compatible 40-Gbit/s selector circuit using resonant tunneling diodes (RTDs) and high-electron-mobility transistors (HEMTs) is presented. The circuit comprises two monostable-bistable transition elements (MOBILEs) using RTDs, a HEMT NOR circuit, and a HEMT output buffer based on source-coupled-FET logic (SCFL). The circuit is fabricated by monolithically integrating RTDs and 0.1-µm HEMTs on an InP substrate. The fabricated circuit exhibits clear eye-opening at 40 Gbit/s with an output swing of 800 mVp-p, which is close to the conventional high-speed logic IC interface called SCFL.