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[Author] Shinji MATSUOKA(5hit)

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  • A Universal Structure for SDH Multiplex Line Terminals with a Unique CMOS LSI for SOH Processing

    Yoshihiko UEMATSU  Shinji MATSUOKA  Kohji HOHKAWA  Yoshiaki YAMABAYASHI  

     
    PAPER-Communication Systems and Transmission Equipment

      Vol:
    E78-B No:3
      Page(s):
    362-372

    This paper proposes a universal structure for STM-N(N=1, 2, 3, ) multiplex line terminals that only utilizes N chips CMOS LSIs for Section OverHead (SOH) processing. The uniquely configured LSIs are applicable to any STM-N line terminal equipment. Reasonable frame alignment performance attributes, such as the maximum average reframe time, false in-frame time, out-of-frame detection time, and misframe time, are calculated for the configuration. A prototype SOH processing LSI built on 0.8m BiCMOS technology successfully realizes the functions needed for multiplex section termination. The STM-64 frame is also demonstrated using the proposed circuit configuration and prototype LSIs.

  • Fault Localization and Supervisory Channel Implementation for Optical Linear-Repeaters in SDH/SONET-Based Networks

    Shinji MATSUOKA  Kazuyuki MATSHUMURA  Yoshiaki SATO  Yukio KOBAYASHI  Kazuo HAGIMOTO  

     
    PAPER-Optical Communication

      Vol:
    E79-B No:10
      Page(s):
    1549-1557

    This paper proposed a fault localization and supervisory (SV) channel implementation for linear-repeaters (L-Reps) employing optical line amplifiers. In order to successfully introduce L-Reps into a Synchronous Digital Hierarchy (SDH)/Synchronous Optical Network (SONET)-based networks in a smooth, orderly fashion, layering of repeater section and supervisory system design must be taken into consideration. There supervisory techniques, such as linking analog-based and digital-based information, a precedence of digital-based information and an upstream precedence, for locating faulty L-Rep sections are proposed taking into consideration the difference in monitoring capabilities between L-Reps and regenerating-type repeaters (R-Reps). Furthermore, a linear repeater supervisory (LSV) channel configuration for L-Reps is also proposed. Finally, an SV system established in a prototype SDH-based 10-Gbit/s optical transmission system is briefly described.

  • Integrated Circuits for Ultra-High-Speed Optical Fiber Transmission Systems

    Kohji HOHKAWA  Shinji MATSUOKA  Kazuo HAGIMOTO  Kiyoshi NAKAGAWA  

     
    INVITED PAPER-LSI Technology for Opto-Electronics

      Vol:
    E76-C No:1
      Page(s):
    68-77

    Optical fiber transmission systems have advanced rapidly with the advent of highly advanced electronic and optical devices. This paper introduces several IC technologies required for ultra-high-speed optical transmission and overviews current IC technologies used for the existing and developing optical fiber trunk transmission systems. Future trends in device technologies are also discussed.

  • Distributed-Controlled Multiple-Ring Networks with Classified Path Restoration

    Masahito TOMIZAWA  Shinji MATSUOKA  Yoshihiko UEMATSU  

     
    PAPER-Communication Networks and Services

      Vol:
    E80-B No:7
      Page(s):
    1000-1007

    This paper provides an architectural study of optical multiple-ring trunk-transmission networks using high-speed Time Division Multiplexing (TDM), and proposes two algorithms for distributed control environments. We propose a path-setup algorithm that uses Token protocol over Section Overhead (SOH) bytes, by which network-nodes communicate with each other to reserve bandwidth. A classified path restoration algorithm is also proposed that offers 3 path classes in terms of restoration performance. Class A paths, the most reliable, never lose any bit even against unpredictable disasters. They are realized by path-duplication at the source node, route diversity,and hitless switching at the destination node. Class B paths are restored by re-routing, where the original path-setup algorithm is reused. Class C paths are the most economical because a failed path is restored by maintenance action.

  • Parallel mB1C Word Alignment Procedure and Its Performance for High-Speed Optical Transmission

    Yoshihiko UEMATSU  Koichi MURATA  Shinji MATSUOKA  

     
    PAPER-Communication Systems and Transmission Equipment

      Vol:
    E80-B No:3
      Page(s):
    476-482

    This paper proposes a parallel word alignment procedure for m Binary with 1 Complement Insertion (mBlC) or Differential m Binary with l Mark Insertion (DmBlM) line code. In the proposed procedure for mBlC line code, the word alignment circuit searches (m+1) bit pairs in parallel for complementary relationships. A Signal Flow Graph Model for the parallel word alignment procedure is also proposed, and its performance attributes are numerically analyzed. The attributes are compared with those of the conventional bit-by-bit procedure, and it is shown that the proposed procedure displays superior performance in terms of False-Alignment Probability and Maximum Average Aligning Time. The proposed procedure is suitable for high speed optical data links, because it can be easily implemented using a parallel signal processor operating at a clock rate equal to 1/(m+1) times the mBlC line rate.