A Jitter Suppression Technique for a Clock Multiplier

Kiyoshi ISHII; Keiji KISHINE; Haruhiko ICHINO

A Jitter Suppression Technique for a Clock Multiplier

Kiyoshi ISHII, Keiji KISHINE, Haruhiko ICHINO

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This paper describes a jitter suppression technique for a clock multiplier IC that uses a phase-locked loop (PLL). It is shown that the jitter cutoff frequency of the jitter transfer function can be greatly improved by adding a surface acoustic wave (SAW) filter whose center frequency equals the input frequency. The jitter transfer function is mainly determined by the characteristics of the SAW filter. Therefore, the clock multiplier IC can be set at a high loop gain to minimize the jitter generation without increasing the jitter cutoff frequency. The use of a clock multiplier IC that was fabricated with Si bipolar technology and a SAW filter with the center frequency of 155.52 MHz and a quality (Q) factor of 1500 results in a very low jitter generation of 3.5 mUI rms and an extremely low jitter cutoff frequency of about 50 kHz when the clock multiplier converts a clock frequency of 155.52 MHz into a 2.48832-GHz signal.

Publication: IEICE TRANSACTIONS on Electronics Vol.E83-C No.4 pp.647-651

Publication Date: 2000/04/25

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Type of Manuscript: PAPER

Category: Integrated Electronics

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Kiyoshi ISHII, Keiji KISHINE, Haruhiko ICHINO, "A Jitter Suppression Technique for a Clock Multiplier" in IEICE TRANSACTIONS on Electronics, vol. E83-C, no. 4, pp. 647-651, April 2000, doi: .
Abstract: This paper describes a jitter suppression technique for a clock multiplier IC that uses a phase-locked loop (PLL). It is shown that the jitter cutoff frequency of the jitter transfer function can be greatly improved by adding a surface acoustic wave (SAW) filter whose center frequency equals the input frequency. The jitter transfer function is mainly determined by the characteristics of the SAW filter. Therefore, the clock multiplier IC can be set at a high loop gain to minimize the jitter generation without increasing the jitter cutoff frequency. The use of a clock multiplier IC that was fabricated with Si bipolar technology and a SAW filter with the center frequency of 155.52 MHz and a quality (Q) factor of 1500 results in a very low jitter generation of 3.5 mUI rms and an extremely low jitter cutoff frequency of about 50 kHz when the clock multiplier converts a clock frequency of 155.52 MHz into a 2.48832-GHz signal.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_4_647/_p

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@ARTICLE{e83-c_4_647,
author={Kiyoshi ISHII, Keiji KISHINE, Haruhiko ICHINO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Jitter Suppression Technique for a Clock Multiplier},
year={2000},
volume={E83-C},
number={4},
pages={647-651},
abstract={This paper describes a jitter suppression technique for a clock multiplier IC that uses a phase-locked loop (PLL). It is shown that the jitter cutoff frequency of the jitter transfer function can be greatly improved by adding a surface acoustic wave (SAW) filter whose center frequency equals the input frequency. The jitter transfer function is mainly determined by the characteristics of the SAW filter. Therefore, the clock multiplier IC can be set at a high loop gain to minimize the jitter generation without increasing the jitter cutoff frequency. The use of a clock multiplier IC that was fabricated with Si bipolar technology and a SAW filter with the center frequency of 155.52 MHz and a quality (Q) factor of 1500 results in a very low jitter generation of 3.5 mUI rms and an extremely low jitter cutoff frequency of about 50 kHz when the clock multiplier converts a clock frequency of 155.52 MHz into a 2.48832-GHz signal.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - A Jitter Suppression Technique for a Clock Multiplier
T2 - IEICE TRANSACTIONS on Electronics
SP - 647
EP - 651
AU - Kiyoshi ISHII
AU - Keiji KISHINE
AU - Haruhiko ICHINO
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2000
AB - This paper describes a jitter suppression technique for a clock multiplier IC that uses a phase-locked loop (PLL). It is shown that the jitter cutoff frequency of the jitter transfer function can be greatly improved by adding a surface acoustic wave (SAW) filter whose center frequency equals the input frequency. The jitter transfer function is mainly determined by the characteristics of the SAW filter. Therefore, the clock multiplier IC can be set at a high loop gain to minimize the jitter generation without increasing the jitter cutoff frequency. The use of a clock multiplier IC that was fabricated with Si bipolar technology and a SAW filter with the center frequency of 155.52 MHz and a quality (Q) factor of 1500 results in a very low jitter generation of 3.5 mUI rms and an extremely low jitter cutoff frequency of about 50 kHz when the clock multiplier converts a clock frequency of 155.52 MHz into a 2.48832-GHz signal.
ER -