We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by rising or falling edges of input data, recover clock signals, which are then combined by a phase interpolator. This configuration reduces the RMS jitters of the recovered clock by 30% and doubles the maximum run length compared to a previously reported DPA CDR. A prototype chip is demonstrated with 0.18-µm CMOS technology. Measurement results show that the chip operates without any bit error for 1.25-Gb/s 231-1 PRBS with 200-ppm frequency offset and recovers clock and data after two clock cycles.

In this paper, a novel 622 Mb/s burst-mode clock and data recovery (CDR) circuits with muxed oscillators are realized for passive optical network (PON) application. The CDR circuits are implemented with 0.35 µm CMOS process technology. Lock is accomplished on the first data transition and data are sampled at the optimal point. The experimental results show that the proposed CDR circuits recover the incoming 400-622 Mb/s burst mode input data without errors.

A new charge pump is proposed which provides improved jitter characteristics for a phase-locked loop (PLL). The PLL with the proposed charge pump is implemented with 0.6 µm CMOS technology. The measured RMS output jitter is as much as 28% smaller than that of a PLL with a previously reported charge pump structure.

A linear model for feedforward ring oscillators (FROs) is developed and oscillator characteristics are analyzed using the model. The model allows prediction of multiple oscillation modes as well as the oscillation frequency of each mode. The prediction agrees well with SPICE simulation results.

A new 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit is realized. To overcome jitter problems caused by the phase resolution limit, the CDR has two phase generation stages: coarse generation by a phase interpolator and fine generation by a variable delay buffer. The performance of the proposed CDR was verified by behavioral and transistor-level simulations. A prototype CDR chip fabricated with 0.18 µm CMOS process shows error-free operation for 400 ppm frequency offset. The chip occupies 165255 µm2 and consumes 17.8 mW.

A new compact line equalizer is proposed for backplane serial link applications. The equalizer has two control blocks. The feed-forward swing control block determines the optimal low frequency level and the feedback control block detects signal shapes and decides the high-frequency boosting level of the equalizer. Successful equalization is demonstrated over a 1.5 m long PCB trace at 3.125-Gb/s by the circuit realized with 0.18 µm CMOS process. The circuit occupies only 0.16 mm2 and consumes 20 mW with 1.8 V supply.

A mixed-mode high-speed binary phase-shift keying (BPSK) demodulator for IEEE802.15.3c mm-wave wireless personal area network (WPAN) application is realized with 0.18-µm CMOS process. The proposed demodulator scheme does not require any analog-to-digital converters (ADC) and, consequently, can have advantages over the conventional schemes for high-data-rate demodulation. The demodulator core consumes 53.8 mW from 2.5-V power supply while the chip area is 380500 µm2. The fabricated chip is verified by 60-GHz wireless link tests with 1.6-Gb/s data.

A new clock and data recovery circuit (CDR) is realized for the application of data communication systems requiring GHz-range clock signals. The high frequency jitter is one of major performance-limiting factors in CDR, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Furthermore, optical characteristics for fast locking are achieved with the adaptive delay cell in the phase detector. The circuit is designed based on CMOS 0.25 µm fabrication process and its performance is verified by measurement results.