Chemical sensor which can be used for a multi-purpose chemical measurement to detect various chemical substances with a small number of a sensor array was investigated. It was confirmed that chemical compounds adsorbed strongly and irreversibly on a platinum surface using conventional electrochemical methods and an instrumental surface analysis. The adsorbates were also analyzed by means of an electrochemical impedance spectroscopy under dynamic potential scan; measured impedance reflects CPE (constant phase element) properties of the electrode surface. The method provides a convenient technique for the surface analysis of adsorbing chemicals. The CPE response profile was modified through chemical adsorption/desorption and the interaction between the polarized surface and chemical substances. Consequently, various profiles depending on chemical substances were obtained and it had quantitative and qualitative information about chemicals interacting with the surface. The present method which does not require a specific electrochemical reaction can be applied for multi-purpose chemical sensors and also simple chemical analyses.

The message passing interface (MPI) broadcast communication commonly causes a severe performance bottleneck in multicore system that uses distributed memory. Thus, in this paper, we propose a novel algorithm and hardware structure for the MPI broadcast communication to reduce the bottleneck situation. The transmission order is set based on the state of each processing node that comprises the multicore system, so the novel algorithm minimizes the performance degradation caused by conflict. The proposed scoreboard MPI unit is evaluated by modeling it with SystemC and implemented using VerilogHDL. The size of the proposed scoreboard MPI unit occupies less than 1.03% of the whole chip, and it yields a highly improved performance up to 75.48% as its maximum with 16 processing nodes. Hence, with respect to low-cost design and scalability, this scoreboard MPI unit is particularly useful towards increasing overall performance of the embedded MPSoC.

We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by rising or falling edges of input data, recover clock signals, which are then combined by a phase interpolator. This configuration reduces the RMS jitters of the recovered clock by 30% and doubles the maximum run length compared to a previously reported DPA CDR. A prototype chip is demonstrated with 0.18-µm CMOS technology. Measurement results show that the chip operates without any bit error for 1.25-Gb/s 231-1 PRBS with 200-ppm frequency offset and recovers clock and data after two clock cycles.

In this paper, a novel 622 Mb/s burst-mode clock and data recovery (CDR) circuits with muxed oscillators are realized for passive optical network (PON) application. The CDR circuits are implemented with 0.35 µm CMOS process technology. Lock is accomplished on the first data transition and data are sampled at the optimal point. The experimental results show that the proposed CDR circuits recover the incoming 400-622 Mb/s burst mode input data without errors.

In this paper, I propose dynamic gamma control (DGC) as a new contrast enhancement technology for liquid crystal displays. Unlike conventional technologies involving the manipulation of digital image data, DGC modifies analog gamma reference voltages in accordance with the image data distribution. A digital gamma buffer (DGB) and a new system architecture were developed for DGC implementation. Experimental results show that DGC can increase the contrast ratio of 5 images twofold on average.

A chirp spread spectrum (CSS) system uses a chirp signal which changes the instantaneous frequency according to time for spreading a transmission bandwidth. In the CSS system, the transmission performance can be simply improved by increasing the time-bandwidth product which is known as the processing gain. However, increasing the transmission bandwidth is limited because of the spectrum regulation. In this letter, we propose a correlation-based chirp rate allocation method to improve the transmission performance by analyzing the cross-correlation coefficient in the same time-bandwidth product. In order to analyze the transmission performance of the proposed method, we analytically derive the cross-correlation coefficient according to the time-bandwidth separation product and simulate the transmission performance. The simulation results show that the proposed method can analytically allocate the optimal chirp rate and improve the transmission performance.

A new 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit is realized. To overcome jitter problems caused by the phase resolution limit, the CDR has two phase generation stages: coarse generation by a phase interpolator and fine generation by a variable delay buffer. The performance of the proposed CDR was verified by behavioral and transistor-level simulations. A prototype CDR chip fabricated with 0.18 µm CMOS process shows error-free operation for 400 ppm frequency offset. The chip occupies 165255 µm2 and consumes 17.8 mW.