This paper presents an explicit analysis of the output error power in wideband sampling systems with finite aperture time in the presence of sampling jitter. Sampling jitter and finite aperture time affect the ability of wideband sampling systems to capture high-frequency signals with high precision. Sampling jitter skews data acquisition timing points, which causes large errors in high-frequency (large slew rate) signal acquisition. Finite sampling-window aperture works as a low pass filter, and hence it degrades the high-frequency performance of sampling systems. In this paper, we discuss these effects explicitly not only in the case that either sampling jitter or finite aperture time exists but also the case that they exist together, for any aperture window function (whose Fourier transform exists) and sampling jitter of Gaussian distribution. These would be useful for the designer of wideband sampling data acquisition systems to know how much sampling jitter and aperture time are tolerable for a specified SNR. Some experimental measurement results as well as simulation results are provided as validation of the analytical results.

This paper describes the nonlinear behavior of CMOS ADC input capacitance. Our SPICE simulation, based on the BSIM3v3 model, shows that the input capacitance of a typical CMOS flash-type ADC (with a single-ended NMOS differential pair preamplifier as the input stage) decreases as its input voltage increases; this is the opposite of what we would expect if we considered only MOSFET gate capacitance nonlinearity. We have found that this can be explained by the nonlinearity of the total effective input capacitance of each differential amplifier stage, taking into account not only MOSFET capacitance but also the fact that the contributions of the gate-source and gate-drain capacitances to the input capacitance of the differential pair change according to its input voltages (an ADC input voltage and a reference voltage). We also discuss design methods to reduce the value of the CMOS ADC effective input capacitance.

We have developed a high-efficiency charge-pump power supply circuit with large output current capability for mobile equipment. However, during the commercialization phase, we found that the large inrush current of 270 mA at charge-pump circuit startup-time could cause problems. In this paper we analyze the mechanism that causes this inrush current, and we propose circuitry to reduce it. We show SPICE simulation and measurement results for our proposed circuitry that confirm its effectiveness. By incorporating this circuitry, startup-time inrush current was reduced to 30 mA.