This paper presents a new technique for modeling High-Voltage lightly-doped-drain MOS (HV MOS) devices accurately with the BSIM3v3 SPICE model. Standard SPICE models do not model the voltage dependency of Rs and Rd in HV MOS devices; this causes large discrepancies between the simulated and measured I-V characteristics of HV MOS devices. We propose to assign physical meanings and values different from the original BSIM3v3 model to three of its parameters to represent the voltage dependency of Rs and Rd. With this method, we have succeeded in highly accurate parameter extraction, and the simulated I-V characteristics of HV MOS devices using the extracted parameters match the measured results well. The relationship between the proposed modeling technique and the physical mechanism of HV MOS devices is also discussed based on measurement and device simulation results. Since our method does not change any model equations of BSIM3v3, it can be applied to any SPICE simulator on which the BSIM3v3 model runs, so we can use SPICE simulation for accurate circuit design of complex circuits using HV MOS devices.

This paper presents a new technique for accurately modeling uni-directional High-Voltage lightly-doped- drain MOS (HV MOS) devices by extending the bi- directional HV MOS model and adopting a new parameter extraction method. We have already reported on a SPICE model for bi-directional HV MOS devices based on BSIM3v3. However, if we apply this bi- directional HV MOS model and its parameter extraction technique directly to uni-directional HV MOS devices, there are large discrepancies between the measured and simulated I-V characteristics of the uni- directional devices. This paper extends the bi- directional HV MOS model, and adopts a new parameter extraction technique. Using parameters extracted with the new method, the simulated I-V characteristics of the uni-directional n-channel HV MOS device match the measured results well. Since our method does not change any model equations of BSIM3v3, it can be applied to any SPICE simulator on which the BSIM3v3 model runs.

This paper describes the nonlinear behavior of CMOS ADC input capacitance. Our SPICE simulation, based on the BSIM3v3 model, shows that the input capacitance of a typical CMOS flash-type ADC (with a single-ended NMOS differential pair preamplifier as the input stage) decreases as its input voltage increases; this is the opposite of what we would expect if we considered only MOSFET gate capacitance nonlinearity. We have found that this can be explained by the nonlinearity of the total effective input capacitance of each differential amplifier stage, taking into account not only MOSFET capacitance but also the fact that the contributions of the gate-source and gate-drain capacitances to the input capacitance of the differential pair change according to its input voltages (an ADC input voltage and a reference voltage). We also discuss design methods to reduce the value of the CMOS ADC effective input capacitance.

This paper presents improved versions of three-stage positive-output and two-stage negative-output Dickson charge-pump circuits which are intended to replace switching regulators in video-product CCD driver applications (where 12 V and -6.5 V are needed), and are designed and fabricated in a custom CMOS process. From a power supply Vdd of 4.0 to 5.5 V, the positive charge pump generates a positive output voltage of greater than 3.9Vdd, while the negative charge pump generates a negative voltage of greater than -1.9Vdd, both with efficiencies of greater than 94% at 2 mA output currents.

We have developed a high-efficiency charge-pump power supply circuit with large output current capability for mobile equipment. However, during the commercialization phase, we found that the large inrush current of 270 mA at charge-pump circuit startup-time could cause problems. In this paper we analyze the mechanism that causes this inrush current, and we propose circuitry to reduce it. We show SPICE simulation and measurement results for our proposed circuitry that confirm its effectiveness. By incorporating this circuitry, startup-time inrush current was reduced to 30 mA.

This paper presents a 0.5Vdd-step pumping method for Dickson-type charge-pump circuits that achieve high overall efficiency, including regulator circuitry, even at large output currents, and these circuits are targeted at mobile equipment applications. We have designed positive and negative charge-pump circuits which use a 0.5Vdd-step pumping method, are implemented with advanced control functions, and are fabricated with our custom CMOS process. Measured results showed that efficiency of a 2.5-stage positive charge-pump circuit before regulation is more than 93% (power supply Vdd=5 V, output voltage Vout=16.9 V 3.5Vdd, output current Iout=4 mA), and that of a 1.5-stage negative charge-pump circuit is 93% (power supply Vdd=5 V, output voltage Vout=-7.2 V -1.5Vdd, output current Iout=4 mA).

This paper describes a simple, inexpensive technique for intentionally broadening and flattening the spectrum of a DC-DC converter (switching regulator) to reduce Electro-Magnetic Interference (EMI). This noise spectrum broadening technique involves intentionally introducing pseudo-random dithering of control clock timing, which can be achieved by adding simple digital circuitry. This technique can significantly reduce noise power spectrum peaks at the DC-DC converter output. For our test case circuit, measurements showed that noise power was reduced by 5.7 dBm at the main peak, by 15.6 dBm at the second peak and by 12.8 dBm at the third peak. This simple, inexpensive technique can be applied to most conventional switching regulators by adding simple digital circuitry, and without any modification of the design of other parts.