This paper describes the nonlinear behavior of CMOS ADC input capacitance. Our SPICE simulation, based on the BSIM3v3 model, shows that the input capacitance of a typical CMOS flash-type ADC (with a single-ended NMOS differential pair preamplifier as the input stage) decreases as its input voltage increases; this is the opposite of what we would expect if we considered only MOSFET gate capacitance nonlinearity. We have found that this can be explained by the nonlinearity of the total effective input capacitance of each differential amplifier stage, taking into account not only MOSFET capacitance but also the fact that the contributions of the gate-source and gate-drain capacitances to the input capacitance of the differential pair change according to its input voltages (an ADC input voltage and a reference voltage). We also discuss design methods to reduce the value of the CMOS ADC effective input capacitance.