Performance Analysis of Oversampling Data Recovery Circuit

Jin-Ku KANG

Performance Analysis of Oversampling Data Recovery Circuit

Jin-Ku KANG

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In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10^-11 BER, 8 times oversampling has about 2 dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits depending on the input data rate and input noise. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5 dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling in white noise dominant input data. The results were applied to the fabricated circuits to validate the analysis.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.6 pp.958-964

Publication Date: 1999/06/25

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Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98))

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Jin-Ku KANG, "Performance Analysis of Oversampling Data Recovery Circuit" in IEICE TRANSACTIONS on Fundamentals, vol. E82-A, no. 6, pp. 958-964, June 1999, doi: .
Abstract: In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10^-11 BER, 8 times oversampling has about 2 dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits depending on the input data rate and input noise. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5 dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling in white noise dominant input data. The results were applied to the fabricated circuits to validate the analysis.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_6_958/_p

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@ARTICLE{e82-a_6_958,
author={Jin-Ku KANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Performance Analysis of Oversampling Data Recovery Circuit},
year={1999},
volume={E82-A},
number={6},
pages={958-964},
abstract={In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10^-11 BER, 8 times oversampling has about 2 dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits depending on the input data rate and input noise. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5 dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling in white noise dominant input data. The results were applied to the fabricated circuits to validate the analysis.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - Performance Analysis of Oversampling Data Recovery Circuit
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 958
EP - 964
AU - Jin-Ku KANG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1999
AB - In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10^-11 BER, 8 times oversampling has about 2 dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits depending on the input data rate and input noise. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5 dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling in white noise dominant input data. The results were applied to the fabricated circuits to validate the analysis.
ER -