This paper presents an adaptive FFE/DFE receiver with an algorithm that measures the data-dependent jitter. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a clock and data recovery phase detector. The receiver is fabricated in with 0.13 µm CMOS technology, and the compensation range of equalization is up to 26 dB at 2 GHz. The test chip is verified for a 40 inch FR4 trace and a 53 cm flexible printed circuit channel. The receiver occupies an area of 440 µm 520 µm and has a power dissipation of 49 mW (excluding the I/O buffers) from a 1.2 V supply.

This paper describes an all-digital DLL (Delay Locked Loop) circuit with a high phase resolution. The proposed architecture is based on three-stage phase tuning blocks for coarse, fine and ultra fine phase control. Each block has a phase detector, a phase selection block and a delay line, respectively. It was simulated in a 0.35 µm CMOS technology under 3.3 V power supply. The simulation result shows the maximum phase error can be reduced to 13-42 ps with the operating range of 250 MHz to 800 MHz.

This letter presents an automatic 2D-to-3D conversion method using a structure from motion (SfM) process for multi-object scenes. The foreground and background regions may have different depth values in an image. First, we detect the foreground objects and the background by using a depth histogram. Then, the proposed method creates the virtual image by projecting each region with its computed projective matrix. Experimental results compared to previous research show that the proposed method provides realistic stereoscopic images.

In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10-11 BER, 8 times oversampling has about 2 dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits depending on the input data rate and input noise. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5 dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling in white noise dominant input data. The results were applied to the fabricated circuits to validate the analysis.

This paper describes a DLL (Delay Locked Loop) circuit with the mixed-mode phase tuning method. The circuit accomplishes unlimited phase shift and accurate phase alignment through the coarse and fine phase tuning technique. It is based on a dual delay locked loop structure. The main loop is for generating coarsely spaced clocks and the second loop is for fast and accurate phase tuning with digital and analog phase detection. Simulations show that this circuit has 360 degree phase shift capability and can resolve 10 ps phase error using 0.6 µm CMOS technology.

This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.