A 4 Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement
Summary :
This paper presents an adaptive FFE/DFE receiver with an algorithm that measures the data-dependent jitter. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a clock and data recovery phase detector. The receiver is fabricated in with 0.13 µm CMOS technology, and the compensation range of equalization is up to 26 dB at 2 GHz. The test chip is verified for a 40 inch FR4 trace and a 53 cm flexible printed circuit channel. The receiver occupies an area of 440 µm
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E94-C No.11 pp.1779-1786
- Publication Date
- 2011/11/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E94.C.1779
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Tae-Ho KIM, Yong-Hwan MOON, Jin-Ku KANG, "A 4 Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 11, pp. 1779-1786, November 2011, doi: 10.1587/transele.E94.C.1779.
Abstract: This paper presents an adaptive FFE/DFE receiver with an algorithm that measures the data-dependent jitter. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a clock and data recovery phase detector. The receiver is fabricated in with 0.13 µm CMOS technology, and the compensation range of equalization is up to 26 dB at 2 GHz. The test chip is verified for a 40 inch FR4 trace and a 53 cm flexible printed circuit channel. The receiver occupies an area of 440 µm
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.1779/_p
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@ARTICLE{e94-c_11_1779,
author={Tae-Ho KIM, Yong-Hwan MOON, Jin-Ku KANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 4 Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement},
year={2011},
volume={E94-C},
number={11},
pages={1779-1786},
abstract={This paper presents an adaptive FFE/DFE receiver with an algorithm that measures the data-dependent jitter. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a clock and data recovery phase detector. The receiver is fabricated in with 0.13 µm CMOS technology, and the compensation range of equalization is up to 26 dB at 2 GHz. The test chip is verified for a 40 inch FR4 trace and a 53 cm flexible printed circuit channel. The receiver occupies an area of 440 µm
keywords={},
doi={10.1587/transele.E94.C.1779},
ISSN={1745-1353},
month={November},}
Copy
TY - JOUR
TI - A 4 Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement
T2 - IEICE TRANSACTIONS on Electronics
SP - 1779
EP - 1786
AU - Tae-Ho KIM
AU - Yong-Hwan MOON
AU - Jin-Ku KANG
PY - 2011
DO - 10.1587/transele.E94.C.1779
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2011
AB - This paper presents an adaptive FFE/DFE receiver with an algorithm that measures the data-dependent jitter. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a clock and data recovery phase detector. The receiver is fabricated in with 0.13 µm CMOS technology, and the compensation range of equalization is up to 26 dB at 2 GHz. The test chip is verified for a 40 inch FR4 trace and a 53 cm flexible printed circuit channel. The receiver occupies an area of 440 µm
ER -
English
