All Digital DLL with Three Phase Tuning Stages
Summary :
This paper describes an all-digital DLL (Delay Locked Loop) circuit with a high phase resolution. The proposed architecture is based on three-stage phase tuning blocks for coarse, fine and ultra fine phase control. Each block has a phase detector, a phase selection block and a delay line, respectively. It was simulated in a 0.35 µm CMOS technology under 3.3 V power supply. The simulation result shows the maximum phase error can be reduced to 13-42 ps with the operating range of 250 MHz to 800 MHz.
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- IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.6 pp.1305-1309
- Publication Date
- 2004/06/01
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003))
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Jin-Ho CHOI, Jin-Ku KANG, "All Digital DLL with Three Phase Tuning Stages" in IEICE TRANSACTIONS on Fundamentals,
vol. E87-A, no. 6, pp. 1305-1309, June 2004, doi: .
Abstract: This paper describes an all-digital DLL (Delay Locked Loop) circuit with a high phase resolution. The proposed architecture is based on three-stage phase tuning blocks for coarse, fine and ultra fine phase control. Each block has a phase detector, a phase selection block and a delay line, respectively. It was simulated in a 0.35 µm CMOS technology under 3.3 V power supply. The simulation result shows the maximum phase error can be reduced to 13-42 ps with the operating range of 250 MHz to 800 MHz.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_6_1305/_p
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@ARTICLE{e87-a_6_1305,
author={Jin-Ho CHOI, Jin-Ku KANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={All Digital DLL with Three Phase Tuning Stages},
year={2004},
volume={E87-A},
number={6},
pages={1305-1309},
abstract={This paper describes an all-digital DLL (Delay Locked Loop) circuit with a high phase resolution. The proposed architecture is based on three-stage phase tuning blocks for coarse, fine and ultra fine phase control. Each block has a phase detector, a phase selection block and a delay line, respectively. It was simulated in a 0.35 µm CMOS technology under 3.3 V power supply. The simulation result shows the maximum phase error can be reduced to 13-42 ps with the operating range of 250 MHz to 800 MHz.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - All Digital DLL with Three Phase Tuning Stages
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1305
EP - 1309
AU - Jin-Ho CHOI
AU - Jin-Ku KANG
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2004
AB - This paper describes an all-digital DLL (Delay Locked Loop) circuit with a high phase resolution. The proposed architecture is based on three-stage phase tuning blocks for coarse, fine and ultra fine phase control. Each block has a phase detector, a phase selection block and a delay line, respectively. It was simulated in a 0.35 µm CMOS technology under 3.3 V power supply. The simulation result shows the maximum phase error can be reduced to 13-42 ps with the operating range of 250 MHz to 800 MHz.
ER -
English
