In this paper, a time-to-digital converter in which the digital output is obtained without delay time is proposed. The circuit consists of a time-to-voltage converter, voltage-to-frequency converter, and counter. In the time-to-voltage converter, a capacitor is charged with a constant current during the input time interval. The change in the capacitor voltage is proportional to the input time and the capacitor voltage can be converted into a pulse signal with the voltage-to-frequency converter. The frequency of the pulse signal is directly proportional to the peak capacitor voltage and the pulse signals are counted to obtain the digital output. In the proposed circuit, the input time interval can be easily controlled and the resolution of the digital output can be improved by controlling the passive devices such as the capacitor and resistor.

This paper describes an all-digital DLL (Delay Locked Loop) circuit with a high phase resolution. The proposed architecture is based on three-stage phase tuning blocks for coarse, fine and ultra fine phase control. Each block has a phase detector, a phase selection block and a delay line, respectively. It was simulated in a 0.35 µm CMOS technology under 3.3 V power supply. The simulation result shows the maximum phase error can be reduced to 13-42 ps with the operating range of 250 MHz to 800 MHz.

In this work, a temperature stable voltage-to-frequency converter (VFC) in which the output frequency is proportional to the input voltage is proposed. The output frequency range is from 22 kHz to 60 kHz and the difference between simulated and calculated values is less than about 5% for this range of output frequency. The temperature variation of sample output frequencies is less than 0.5% in the temperature range -25C to 75C.