In this paper, we describe statistical properties of timing jitter of symbol timing recovery circuit for carrierless amplitude/phase modulation (CAP)-based very high-rate digital subscriber line (VDSL) system. Analytical expressions of the timing jitter for envelope-based timing recovery system, such as squarer-based timing recovery (S-TR) and absolute-value-based timing recovery (A-TR) schemes, are derived in the presence of additive white Gaussian noise (AWGN) or far-end crosstalk (FEXT). In particular, the analytical and simulation results of the timing jitter performance are presented and compared for a 51.84 Mb/s 16-CAP VDSL system. The A-TR system implemented digitally meets the DAVIC's VDSL system requirement, which specifies the maximum peak-to-peak jitter value of 1.5 nsec and the acquisition time of 20 msec.

We present a carrier and sampling frequency offset estimation and compensation scheme for a multi-band orthogonal frequency division multiplexing (MB-OFDM) ultra-wideband (UWB) modem. We first perform initial carrier frequency offset (CFO) estimation and compensation during the preamble period, and then conduct the estimation and compensation of the residual CFO and sampling frequency offset (SFO) during the payload period. The proposed design scheme reduces the logic gate count of the frequency offset compensation block by about 10%, while it gives almost the same performance at the packet error rate (PER) of 10-4 in the CM1 channel. The frequency offset estimation and compensation block is implemented using 90 nm CMOS technology and tested.